Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Samsung Display Co., Ltd.

Jin-Soo Lim

Dong-Hack Suh

Hansoo Kim

Byoungkeun Son

Sung-Il Chang

Changhyun Lee

Ji-Ho Kim

Song-Ho Kim

Jin-Sik Choi

Sun-Hyun Choi

Sunil Shim

Jaehoon Jang

Jin-Sung Lee

Wonseok Cho

Woonkyung Lee

Kwang-Soo Seol

Byung-Kwan You

Dae-Beom Kim

Jin-Yong Oh

Ki-Hyun Kim

Jae-Goo Lee

Youngwoo Park

Han-Soo Kim

Young-Woo Park

Kwang Soo Seol

Chang-seok Kang

Young-woo Park

Seong Soon Cho

Jae-Hun Jeong

Byeong-In Choe

Taekyung Kim

Ju-Young Lim

Vladimir Urazaev

Jin Ha Jeong

Sung-Hwan Jang

Chi-Hun Kim

Hyunchul Back

Dew-ill Chung

Jong In Yun

Heayun Lee

Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Three dimensional semiconductor devices

A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Semiconductor device

A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Method of manufacturing three-dimensional semiconductor memory device in which an oxide layer is formed at bottom of vertical structure of the device

A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.

Vertical type semiconductor device and method for manufacturing the same

Three-dimensional semiconductor devices and methods of fabricating the same

Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Methods of manufacturing vertical semiconductor devices

The present invention relates to an organic electroluminescence device containing a light emitting metallic compound of Chemical Formula 1. In the Chemical Formula 1, M is selected from Ir, Pt, Rh, Re, and Os, and m is 2, provided that m is 1 when M is Pt.

Metallic compound and organic electroluminescence device comprising the same

Three-dimensional semiconductor devices

A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.

Three dimensional semiconductor memory devices and methods of fabricating the same

A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.

Vertical structure nonvolatile memory devices

Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.

Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices

A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.

Method of fabricating non-volatile memory device having vertical structure

The present invention relates to a light emitting binuclear transition metal compound of Chemical Formulae 1 and 2, and an organic electroluminescence device including the compound. In the Chemical Formulae 1 and 2, M is selected from Ir, Pt, Rh, Re, and Os, and m is 2, provided that the m is 1 when M is Pt.

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Seoul, South Korea

Jin-Soo Lim