Samsung Electronics Co., Ltd.

Jin-seok Lee

Dong-kyun Kim

Bong-hee Lee

Sang-seok Kang

Sang-uk Jeon

Jong-hyoung Lim

Jae-hoon Joo

Chang-hag Oh

Jeon-hyung Lee

A fusing apparatus to fuse a toner image transferred to a printing medium by applying heat and pressure. The fusing apparatus includes a separation member that is rotatably mounted on a rotation axis to separate the printing medium from one of a heating roller and a pressing roller. The separation member includes a hollow portion into which the rotation axis is inserted, and a separation portion that contacts an outer circumference of the heating roller. The separation member is installed so as to be pitched around the rotation axis and a pitching axis having an inclination angle within a range of &#xb1;10&#xb0; with respect to a line that connects a contact point between the separation portion and the outer circumference of the roller from which the printing medium is to be separated and a center of the roller from which the printing medium is to be separated.

Fusing apparatus and electrophotographic image forming apparatus using the same

An image forming apparatus includes a heat roller heated to a preset temperature; a pressure roller for having conductivity and forming a nip by pressure-contacting with the heat roller; a power supply unit to apply a bias voltage to the pressure roller; and a controller to, when a printing paper enters the nip, control the power supply unit to apply the bias voltage to the pressure roller. When a time interval is longer than a preset time, the controller can control the power supply unit not to apply the bias voltage when the printing paper is not placed in the nip, and when the time interval is shorter than the preset time, the controller can control the power supply unit to apply the bias voltage when the printing paper is not placed in the nip.

Image forming apparatus and method for controlling fuser thereof

An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell. The internal voltage supply varies responsive to changes in resistance values.

Circuit for converting internal voltage of semiconductor device

Integrated circuit memory devices contain an array of active memory cells and at least one column of dummy memory cells having missing electrical connections to either a dummy bit line and/or respective storage electrodes. The dummy memory cells are provided with missing electrical connections so that formation of stray electrical 'shorts' between storage electrodes of dummy and active memory cells during fabrication do not cause memory failures when the memory devices are installed. In particular, integrated circuit memory devices are provided which comprise an array of active DRAM memory cells and a column of dummy DRAM memory cells. The active DRAM memory cells each contain electrical connections to a respective active bit line and a respective storage electrode, but the dummy DRAM memory cells are each devoid of an electrical connection to a dummy bit line and/or a respective storage electrode. Accordingly, the formation of a stringer (e.g., electrical short) between a storage capacitor of an active memory cell and a dummy memory cell does not result in a memory failure even if the word line coupled to the dummy memory cell is activated and the dummy bit line is biased at a potential which is different from the potential of the storage capacitor of the active memory cell.

Growing community of inventors

Suwon-si, South Korea

Jin-seok Lee