Samsung Electronics Co., Ltd.

Jin-Seok Kwak

Seong-Jin Jang

Young-Hyun Jun

Sang-Bo Lee

Min-Sang Park

Chul-Soo Kim

Yong-ho Shim

A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

Semiconductor memory device capable of reading and writing data at the same time

Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence. For memory bank selected prior to a last selected memory bank in the predetermined sequence, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P, and for the last selected memory bank, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P, wherein Pis greater than P. A switching unit sequentially connects each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period Por P, in response to the corresponding bank selection control signals.

Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method

A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal in synchronization with each other. The memory circuit, which can be an SDRAM memory circuit, receives the data strobe signal and the data load signal and writes data in response to the two synchronous signals. Because the signal are synchronous, parameters introduced by timing variations caused by different signal domains are eliminated. As a result, high-frequency operation of the system is greatly improved.

Semiconductor memory device having external data load signal synchronous with data strobe signal and serial-to-parallel data prefetch method thereof

A system and method allows for multiple modes of termination, including termination by a fixed value that is preprogrammed, and by a variable value that can, for example, be measured and determined by a self-calibration circuit. Multiple termination values can be achieved within a single device. This configuration is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.

Circuit and method for controlling on-die signal termination

A data output circuit and method in a synchronous semiconductor device are described. The semiconductor device is preferably a wave pipelined synchronous semiconductor device. A first-stage or former-stage latch unit receives a first bit of a group of data bits to be output. A second-stage or latter-stage latch unit receives a second bit of the group of data bits. A buffering unit is interposed between the first and second stage latch units. The buffering unit receives the second bit from the second-stage latch unit and forwards the second bit to the first-stage latch unit.

Circuit and method for data output in synchronous semiconductor device

A semiconductor memory device having a write masking function and a write masking method are provided. The semiconductor memory device includes a plurality of write bit lines, a plurality of write word lines, a plurality of write drivers, a plurality of MOS transistors, a plurality of latch circuits, and a plurality of precharge controllers. Each of the write drivers receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated. Each of the latch circuits includes an inverter having a large driving capacity and an inverter having a small driving capacity. When a precharge signal is activated, each of the precharge controllers precharges a corresponding write bit line to the logic threshold voltage of the inverter having the large driving capacity. Accordingly, memory cells are reliably masked in a write masking mode.

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Suwon, South Korea

Jin-Seok Kwak