Samsung Electronics Co., Ltd.

Jin Seok Kwak

Jong Hyun Choi

Seong Jin Jang

A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase.

Semiconductor memory device and method of driving the same

In a semiconductor memory device that includes memory cell array banks, memory cell array blocks in each memory cell array bank, partial blocks in each memory cell array block, data input/output line pairs connected to the partial blocks, and a predetermined number of redundant partial blocks connected to a predetermined number of redundant data input/output line pairs, the semiconductor memory device further includes an address setting circuit to set a redundant control signal and a defect address of each of the memory cell array blocks, decoder and shifting control signal generating circuits to generate shifting control signals to control shifting of the data input/output line pairs and the predetermined number of redundant data input/output line pairs by decoding the redundant control signal and the defective address, and switching circuits for routing data through data input/output line pairs adjacent to a corresponding data input/output line pairs in response to each of the shifting control signals. Therefore, the semiconductor memory device can generate the shifting control signals dynamically to column cycle and can construct a redundancy circuit with a small number of fuses.

Semiconductor memory device and redundancy method thereof

A redundancy circuit of a semiconductor memory device includes a mode setting circuit that generates mode signal, an input selecting circuit that generates selecting signal in response to the mode signals, and a decoding circuit that, in response to the mode selecting signals, generates decoding signals. The redundancy mode signals include a bank redundancy mode signal, an array redundancy mode signal, and a column address group redundancy mode signal. The selecting signal identifies a bank in bank redundancy mode, an array in an array redundancy mode, and a column address group in column address group redundancy mode. The decoding signals initiate a replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device. A redundancy method includes: generating the redundancy mode signals; generating the selecting signal in response to the redundancy mode signals; and generating the decoding signals.

Redundancy circuit and redundancy method for semiconductor memory device

A precharging apparatus and method is applicable to a semiconductor device having a stack bank-type structure. The device comprises a plurality of memory cell array banks, a plurality of memory cell array blocks of each memory cell array bank comprising a predetermined number of partial blocks connected respectively to the predetermined number of groups of the plurality of partial local data input/output line pairs, in turn connected respectively to the predetermined number of groups of the plurality of global data input/output line pairs, a plurality of switching means which are connected respectively between the predetermined number of groups of the plurality of partial local data input/output line pairs and which are used to connect the predetermined number of groups of the plurality of partial local data input/output line pairs in response to a precharge signal, and a predetermined number of precharge means to precharge the predetermined number of groups of the plurality of partial local data input/output line pairs of each memory cell array block in response to the precharge signal. In this manner, the overall chip size can be reduced by reducing the number of transistors used during a precharge operation.

Growing community of inventors

Hwasung-si, South Korea

Jin Seok Kwak