Samsung Electronics Co., Ltd.

Jin-seok Kwak

Seong-Jin Jang

Joung-Yeal Kim

Jung-bae Lee

Min-Sang Park

Sang-Yun Kim

Chul-woo Yi

Sang-kyun Park

Tai-Young Ko

Young-Hyun Jun

Young-Hun Kim

Dong-Hak Shin

Seong-jin Jang

A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Memory device from which dummy edge memory block is removed

A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell

A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

Semiconductor memory device including signal controller connected between memory blocks

Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same

A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation. Preferably, the first termination impedance is less than the second termination impedance, and the selective ODT circuits provide the first termination impedance responsive to the memory write operation irrespective of which of the first and second memory devices is being written to.

Memory devices, systems and methods using selective on-die termination

Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the inverted version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data

A first clock signal is processed to produce a second clock signal that lags the first clock signal by a first predetermined time and a third clock signal that leads the first clock signal by a second predetermined time. A synchronous read status signal generator circuit receives a read initiation signal indicative of initiation of a read operation and a read termination signal indicative of termination of the read operation. The synchronous read status signal generator circuit produces a transition in a read status signal in response to assertion of either of the read initiation signal or the read termination signal, and latches the read status signal responsive to the second clock signal to generate a synchronized read status signal. A latency signal generator circuit receives the synchronized read status signal and generates a latency control signal therefrom responsive to the third clock signal. Output of data from the memory device is controlled responsive to the latency control signal.

Synchronous memory devices with synchronized latency control circuits and methods of operating same

An MML integrated circuit device includes a memory block, a logic circuit and a buffer memory, and a selection circuit that is coupled between the logic circuit and the buffer memory. The first selection portion is responsive to external data and to the logic circuit, to transmit external data or data from the logic circuit to the memory block via the buffer memory. Thus, MML integrated circuit devices can use the buffer memory to access the memory block during a normal operational mode and during a test mode. MML integrated circuit devices also preferably include a data expansion portion that is coupled between the external data and the selection portion, to replicate the external data a predetermined number of times and to transmit the replicated external data to the selection portion. Errors may be detected in an MML integrated circuit device that includes a memory block, a logic circuit and a buffer memory, by storing external data from external of the MML integrated circuit device into the buffer memory, and storing the external data from the buffer memory into the memory block. The external data is read from the memory block and the read external data is stored from the memory block into the buffer memory. The read external data is output from the buffer memory to external of the MML integrated circuit device. The external data may be stored from external of the MML integrated circuit device into the buffer memory by applying external data from external of the MML integrated circuit device to the MML integrated circuit device, replicating the external data a predetermined number of times in the MML integrated circuit device and storing the replicated external data in the buffer memory.

Merged memory and logic (MML) integrated circuit devices including buffer memory and methods of detecting errors therein

Integrated circuit memory devices having merged data test capability include first and second memory cell arrays in first and second blocks of memory, respectively, a first global input/output line and switches for enabling transfer of data from the first memory cell array to the first global input/output line in response to a first merged data test control signal P1 and enabling transfer of data from the second memory cell array to the first global input/output line in response to a second merged data test control signal P2. A highly integrated merged data test circuit is also provided with test cells therein and each test cell is capable of testing multiple memory cell arrays in at least two blocks of memory. A first merged data test circuit is provided which has a first input electrically coupled to the first global input/output line and a first output which generates first and second error signals upon detection of a failure in the first and second memory cell arrays, respectively.

Integrated circuit memory devices having highly integrated merged data

An integrated circuit having a wide internal data path, such as a Merged Memory and Logic (MML) integrated circuit, is tested by serially comparing data on one of the data paths to data on selected others of the data paths. A first indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value. A second indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value. A third indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values. By serially comparing data on one of the data paths to data on selected others of the data paths, a reduced number of comparators may be provided. Efficient circuits and methods for testing integrated circuits, such as memory integrated circuits or logic integrated circuits, may thereby be provided.

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Hwaseong-si, South Korea

Jin-seok Kwak