Samsung Electronics Co., Ltd.

Jin-Seok Heo

Jung-Hwan Choi

Chang-Kyo Lee

Yoo-Chang Sung

Ju-Ho Jeon

Wang-Soo Kim

Ki-Duk Park

Jin-Sung Youn

Kyung-Soo Ha

Chang-min Park

Jeong-Ho Yeo

Ki-Ho Kim

Seok-Hun Hyun

Seong-Hwan Jeon

In-Dal Song

Seok-Hwan Oh

Joung-Wook Moon

Jin-Hyeok Baek

A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Memory modules, memory systems and methods of operating memory modules

A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.

Memory device determining operation mode based on external voltage and method of operating the same

A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

Data alignment circuit of a semiconductor memory device, a semiconductor memory device and a method of aligning data in a semiconductor memory device

A method of manufacturing a mask includes dividing an upper surface of a template having a design pattern into a plurality of regions, the template being arranged over a polymer layer on a mask substrate, correcting a distorted region among the regions, pressing the polymer layer with the template to form a mask pattern corresponding to the design pattern on the polymer layer; and curing the mask pattern.

Method of manufacturing a mask

Growing community of inventors

Jeonju-si, South Korea

Jin-Seok Heo