Hyundai Electronics Industries Co. Ltd.

Hyundai Electronics Ind. Co., Ltd.

Hyundai Electronics Industries

Jin San Park

Jun M Kim

Seung H Park

Jae Hak Shin

Hyun Kwan Lee

Choong Hoo Kim

Soo Woong Hwang

A circuit for driving a LCM, comprising: a power supply portion for receiving an external voltage of 12V to generate internal voltages of 3.3V and 5V; a clock generation portion for generating a clock signal of desired frequency; a driving signal generation portion for receiving the clock signal from the clock generation portion to generate driving signals of a data enable signal, a horizontal synchronous signal, a vertical synchronous signal, and an enable signal; a signal selection portion for selecting the desired signals of the driving signals from the driving signal generation portion and outputting the selected driving signals and the clock signal from the clock generation portion; a state detection portion for receiving the vertical synchronous signal and the external voltage of 5V to detect a normal operation state of the LCM; a power selection portion for selecting one of an external voltage of 5V and the external voltage of 12V in accordance with application of the internal voltage of 5V; and an output portion for outputting the selected driving signals and clock signal from the signal selection portion, the selected power voltage from the power selection portion and a state detection signal from the state detection portion.

Liquid crystal display module driving circuit

Disclosed is a thin film transistor liquid crystal display capable of fast operation and having enhanced display quality. The thin film transistor liquid crystal display comprises a transparent insulating substrate; gate lines and storage lines arranged on the transparent insulating substrate in rows parallel to each other alternatively; data lines arranged in columns perpendicular to the gate lines and the storage lines so as to define pixel areas; a first pixel area defined by a pair of gate lines and a pair of data lines, and a second pixel area defined by a pair of storage lines and a pair of data lines; and a first thin film transistor disposed adjacent to an intersection of the gate line and the data line and in contact with the first pixel electrode on an upper position, and a second thin film transistor disposed adjacent to an intersection of the storage line and the data line and in contact with the second pixel electrode on a lower position.

LCD having TFT formed at an intersection of data and capacitor lines

The invention disclosed relates to a facsimile transmission/reception method and apparatus using a common bus in an office automation system, and in detail to a facsimile transmission/reception method and apparatus using a single common bus for transmitting and receiving data and control signals to be interfaced with the outer devices. The apparatus comprises a decoding means 31 being applied with a scanning output data chip selection signal CS1 and a liquid crystal display chip selection signal CS2 for decoding a corresponding selection output signal, a selection output means 34,35 controlled by a first and second storage means 32 and 33 latching data, control signals and the like and the decoding means for selectively outputting the data latched by the first and the second storage means, and a common bus 37 for transmitting the data outputted by the selection output means to the operation panel unit 40. Accordingly, use of a common bus for the data, control signals or the like applied from the external devices will reduce the number of signal lines, enhancing capability of miniaturization of the equipment and adoption of measures against radiative interferences.

Facsimile transmission/reception method and apparatus using a common bus

An image processing apparatus useful in, for example, FAX machines, for processing a binary or multiple level tone data in an image including a switch for selectively outputting either a binary level or the multiple level tone pattern in accordance with a selection signal the state of which is determined by the interline reading interval times while scanning the image on an original document. The image processing apparatus includes a temporary storage register for storing a digital binary or multiple level tone pattern, and a selection switch controlled by a binary/multiple level tone selection signal for selectively coupling to the maximum voltage reference input of an analog-digital converter an output signal either from a background color compensator when the binary/multiple level tone selection signal indicates binary level tone image processing is occurring or a voltage value established by a first voltage divider whose resistor values are predetermined according to output voltage levels from the image sensor during multiple level tone image scanning. The digital-analog converter converts binary or multi-level tone pattern data output from temporary storage register into an analog signal using a minimum voltage reference established by a second voltage divider which has resistor values selected in accordance with the minimum output levels from the image sensor. The analog signal from the digital-analog converter is converted to a voltage and compared in a comparison calculator to generate digital data representing the scanned image.

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Songnam, South Korea

Jin San Park