Samsung Electronics Co., Ltd.

Jin-man Han

Jei-Hwan Yoo

Moon-hae Son

Kye-Hyun Kyung

Jung-Hwa Lee

Choong-Sun Shin

Hyung-Dong Kim

Gyu-hong Kim

Dong-il Seo

Se-jin Jeong

Jung-hwa Lee

Il-Jae Cho

At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.

Integrated circuit memories and power distribution methods including at

A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off. The isolation gate control circuit includes a plurality of latches, a plurality of block select signal drivers and a plurality of isolation gate control signal generators.

Method and circuit for controlling an isolation gate in a semiconductor

A signal line driver operating at high speed and consuming low power and a semiconductor memory device employing the same are disclosed. The signal line driver includes one or more first pull-up transistors, one or more second pull-up transistors, and one or more pull-down transistors. The first pull-up transistor is connected between an external power supply terminal and an output terminal and responds to a first control signal which swings between an internal power supply voltage and a ground voltage. The external power supply terminal receives an external power supply having a voltage level higher than the voltage level of the internal power supply. The first pull-up transistor provides an output signal to the output terminal having the voltage level of the internal power supply voltage minus a predetermined voltage drop. The second pull-up transistor is connected between the internal power supply voltage terminal and the output terminal. The internal power supply terminal receives the internal power supply. The second pull-up transistor increases the voltage level of the output signal to the voltage level of the internal power supply responsive to a second control signal. The pull-down transistor is connected between the output terminal and the ground voltage. The pull-down transistor provides a ground voltage to the output terminal responsive to a third control signal. The semiconductor memory device includes an input buffer, an output buffer, a data input/output line write driver, an input/output line write driver, a data input/output line read driver, and a memory cell array. At least one of the drivers for the semiconductor memory device includes the signal line driver described above.

High speed and low power signal line driver and semiconductor memory

A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled. The predecoded row address sampling pulse generator receives the output of the row address strobe buffer and produces a predecoded row address sampling pulse signal for selecting the predecoded row address signal while the first control signal is enabled. The row decoder receives the output of the predecoded row address sampling pulse generator and the row predecoder and has its output connected to a word line and activates the word line when the predecoded row address signal and the predecoded row address sampling pulse signal are enabled.

Row address control circuits having a predecoding address sampling pulse

The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a 'don't care,' and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line. The column redundancy circuit includes: transmitting means comprised of the data input/output lines for transmitting the data of the memory cell; column decoder and input/output control circuits connected to the transmitting means and decoding a column address input to input data; a circuit connected to the transmitting means and outputting a given signal to the column decoder and input/output control circuits in response to a plurality of output signals output from fuses and a signal for controlling the transmitting means; a plurality of decoded fuse circuits, the levels of which are determined by one fuse connected to the circuit; multiplexers for selectively transmitting data from one of the data input/output lines to a specific data bus line among a plurality of data bus lines; and a decoding circuit which receives the outputs of the decoded fuse circuits and generates a redundancy signal.

Column redundancy circuit for a semiconductor memory device

Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Address buffers of semiconductor memory device

A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated with each memory cell. A current path supplies current to each memory cell through the switch associated with each memory cell. A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell. Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.

Standby current detecting circuit for use in a semiconductor memory

An integrated circuit memory device includes a plurality of memory cells, a plurality of data lines, a memory cell selector, and a memory cell connector. The memory cells are arranged in a matrix of rows and columns wherein the plurality of memory cells are further grouped in banks with each bank including at least two rows of memory cells. Each of the data lines extends along one of the columns of memory cells so that each of the data lines extends along memory cells from each of the banks of memory cells. The memory cell selector includes a row decoder which selects one of the plurality of rows, a column decoder which selects one of the plurality of columns, and a bank decoder which selects one of the banks. The connector connects one of the memory cells to a respective data line in response to the memory cell selector. Accordingly, data from only one of the memory cells is provided on a respective one of the data lines at any point and time.

Integrated circuit memory device including banks of memory cells and

An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.

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Seoul, South Korea

Jin-man Han