Micron Technology Incorporated

Tram, Inc.

Round Rock Research, LLC

T-ram Semiconductor, Inc.

Silicon Magic Corporation

Jin-Man Han

Aaron S Yip

Benjamin S Louie

Xiaojun Yu

Hagop A Nazarian

Dzung Huu Nguyen

Seong-Ook Jung

Sei-Seung Yoon

Yunqiu Wan

Farid Nemati

Paul M-Bhor Chiang

Hung-Mao Lin

Seong-Ook Jeong

Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

Method of storing data on a flash memory device

Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

Erase operation control sequencing apparatus, systems, and methods

The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.

Wordline voltage transfer apparatus, systems, and methods

A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Programming memory devices

Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Memory with interleaved read and redundant columns

Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.

Delayed activation of selected wordlines in memory

A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Non-volatile memory device with both single and multiple level cells

The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.

Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect

Flash memory device with redundant columns

A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Growing community of inventors

Santa Clara, CA, United States of America

Jin-Man Han