Yangtze Memory Technologies Co., Ltd.

Jin Lyu

Gang Liu

Kai Jin Huang

Kaijin Huang

Li Hong Xiao

Jun Chen

Zhenyu Lu

Jifeng Zhu

Yushi Hu

Qian Tao

Xiaowang Dai

Jin Wen Dong

Lan Yao

A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The first drain dummy line voltage is greater than the first DSG voltage.

Memory device and program operation thereof

In certain aspects, a memory device includes a first memory string including a first drain, a first drain select gate (DSG) transistor, first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor. The memory device also includes a first bit line coupled to the first drain, a first drain dummy line coupled to the first drain dummy transistor, a first DSG line coupled to the first DSG transistor, word lines respectively coupled to the first memory cells, and a peripheral circuit configured to perform a program operation on a target memory cell of the first memory cells coupled to a selected word line of the word lines. To perform the program operation, the peripheral circuit includes a bit line driver coupled to the first bit line and configured to apply a first bit line voltage to select the first bit line, and a word line driver coupled to the first drain dummy line and the first DSG line and configured to apply a DSG voltage to the first DSG line to turn on the first DSG transistor, and apply a drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The drain dummy line voltage is greater than the DSG voltage.

A three-dimensional (3D) memory device is provided and includes a substrate, an alternating stack and a channel structure. The alternating stack is disposed on the substrate, and the alternating stack includes a plurality of conductive layers and a plurality of air gap layers alternately stacked. The channel structure is disposed on the substrate and extends vertically through the conductive layers and the air gap layers. The alternating stack further includes a plurality of etching stop blocks between the air gap layers and the channel structure.

Three-dimensional memory device and method for manufacturing the same

An operation method for a 3D NAND flash having a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of layers, the operation method includes defining a plurality of upper layers of the plurality of bit lines of the 3D NAND flash as a plurality of upper select gates and a top layer of the plurality of bit lines of the 3D NAND flash as a top dummy layer; and applying a first voltage on a first top dummy layer of a select bit line of the plurality of bit lines to turn on the first top dummy layer of the select bit line of the plurality of bit lines when programming.

Operation method for 3D NAND flash and 3D NAND flash

A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.

Growing community of inventors

Wuhan, China

Jin Lyu