Lsi Corporation

Oracle America, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Storage Technology Corporation

Jin Lu

Shaohua Yang

Weijun Tan

Jeffrey Paul Grundvig

Richard Rauschmayer

Keith Gary Boyer

Yu Liao

Haitao Xia

Richard A Gill

Mark Hennecken

Edward J D'Avignon

A data dependent equalizer circuit includes a plurality of noise prediction filters. Respective ones of the noise prediction filters are configured to filter noise in sample data for at least one predetermined non-return to zero (NRZ) condition. A plurality of equalizers is communicatively coupled with the plurality of noise prediction filters. Respective ones of the plurality of equalizers are configured to yield equalized sample data that corresponds to the at least one predetermined NRZ condition for one or more of the noise prediction filters.

Data-dependent equalizer circuit

Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Systems and methods for multi-head servo data processing

Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Systems and methods for multi-head separation determination

Systems, methods, devices, circuits for transition based equalization.

Systems and methods for transition based equalization

A servo system includes multiple interpolators operable to interpolate equalized data for multiple signal paths in a two dimensional magnetic recording system to yield interpolated signals at different phases, scaling circuits operable to scale the interpolated signals by adaptive scaling factors, a signal combining circuit operable to combine the scaled signals, a phase tracking circuit operable to select one of the phases of the combined signal, and an error gradient circuit operable to adapt the adaptive scaling factors.

Two dimensional magnetic recording servo system adaptive combination

An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output of the decoder configured to perform an iterative decoding process using the set of soft outputs, hard decision information and reliability indicators to determine a decoded data signal; and a multiplexer with a first input coupled to an output of the decoder, a second input coupled to an output of the detector, and an output coupled to an input of the equalizer. The hard decision information is used to train the equalizer.

Equalization combining outputs of multiple component filters

An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize an oversampled digital data signal to determine an equalized digital data signal, filter the equalized digital data signal, determine a hard decision and reliability of the filtered digital data signal, and decode the filtered digital data signal based at least in part on the hard decision and reliability. The oversampled digital data signal comprises a first set of sampled digital data and a corresponding second set of sampled digital data, each of the samples in the first set of sampled digital data being offset from a corresponding one of the sample in the second set of sampled digital data by a phase difference.

Over-sampled signal equalizer

The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.

Systems and methods for data processing including pre-equalizer noise suppression

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.

Systems and methods for parameter modification during data processing retry

A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.

Cycle slip detection and correction

An LDPC coding system includes a number of LDPC encoders and a number of LDPC decoders. The number of encoders/decoders is between one and one fewer than the total number of tracks on the high density tape are provided. The LDPC encoders are operable to break data from an incoming data sector into the data blocks to be written to the high density tape. The LDPC decoders are operable to assemble the data blocks into data sectors.

High density tape drive multi-channel low density parity check coding control

A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out ('FIFO') memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory.

Auxiliary path iterative decoding

A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.

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Lafayette, CO, United States of America

Jin Lu