Texas Instruments Corporation

Jin Liu

Emily Ann Donnelly

Pamula Jean Jones-Williams

Jianglin Wang

Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits.

Self-isolating mixed design-rule integrated yield monitor

According to one embodiment, a method of analyzing semiconductor test data includes receiving a plurality of raw data entries from a testing system. Each raw data entry is associated with a test structure of a semiconductor device, and each raw data entry is uniquely identified by a name including a plurality of parseable fields. The plurality of data entries is parsed using a selected one of the plurality of parseable fields to identify a grouping of raw data entries. At least one reportable parameter indicative of the functionality of the test structures associated with the grouping of raw data entries is calculated, and the at least one reportable parameter is provided to a user.

System and method for the analysis of semiconductor test data

The present invention provides an integrated circuit testing deviceand a method of using the same. In one particular embodiment, the integrated circuit testing device may include a first circuit layerlocated over a semiconductor substrate, wherein the first circuit layerhas a second circuit layerlocated thereover. The integrated circuit testing deviceof the same embodiment may further include a signal bond padselectively connectable to each of the first and second circuit layersto test at least one device on each of the first and second circuit layers

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Southlake, TX, United States of America

Jin Liu