Samsung Electronics Co., Ltd.

Jin-kwon Park

Jae-shin Lee

Cheon-su Lee

Min-joung Lee

A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.

System on chip (SoC) device verification system using memory interface

Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit. Therefore, power can be efficiently managed since power that is supplied to the chips of the SIP semiconductor device is managed by the alive blocks or the local interfaces of the chips.

System in package semiconductor device suitable for efficient power management and method of managing power of the same

An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.

Interface device and inter-chip communication interface apparatus to control data transfer between chips

A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB).

Pin configuration changing circuit, base chip and system in package including the same

Provided are an embedded micro computer unit (MCU) using a memory emulation module and a method of testing the embedded MCU. The embedded MCU includes an internal memory that is connected to bus master devices for storing temporary data of the bus master devices and a test vector in a test mode, a memory controller for accessing the internal memory or an external memory when a processor core is operated, and a memory emulation module that is connected between the memory controller and the internal memory for storing the test vector in the internal memory in the test mode.

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Suwon-si, South Korea

Jin-kwon Park