Hyundai Electronics Industries Co. Ltd.

Jin Kook Choi

Suk Joong Lee

A circuit for controlling the threshold voltage in a semiconductor device. The circuit includes a substrate bias sensing block, and oscillater, a charge pump and a current supplying transistor. The substrate bias sensing block prevents substrate bias from decreasing below a predetermined value and includes a voltage divider including a plurality of PMOS transistors coupled in series between a power supply and the substrate bias, wherein each first junction of each transistor is connected with the substrate and each second junction with each gate. The block includes a latch being applied by the voltage of the first junction of one of the PMOS transistors and the inverted voltage of the corresponding second junction. A very low subthreshold leakage current can be obtained by maintaining a high threshold voltage in the standby mode, and low power consumption and high speed operation can be accomplished by lowering the threshold voltage with the low supplied power in the operation mode.

Circuit for controlling the threshold voltage in a semiconductor device

The present invention relates to a cache Static Random Access Memory, and includes an SRAM cell array unit having a 4 way.times.64 set cell array structure; a write circuit unit for renewing one bit line of 4 way.times.64 set SRAM cell array after receiving a read way selection signal(tRway) applied from a cache controller, and an address applied from a memory management unit, a pre-charge unit for charging a bit line of SRAM cell array unit to a logic high state; a word line decoder unit for selecting one row of 64 rows of an SRAM cell array unit; a sense amplifier unit for amplifying a weak signal which is, via a bit line, read from a cell of a row selected by the word line decoder unit; a comparator unit for outputting a signal(Taghit#0) by comparing an address applied from the write circuit unit with an output of the sense amplifier unit; and a test circuit for calculating and then outputting a node(AA) value, which is used for determine as to whether or not an SRAM cell is normal according to two signals Dphi1b and Phi2 after receiving data read from the SRAM cell array via the sense amplifier unit and a read way selection signal(tRway) applied from a cache controller.

Cache static RAM having a test circuit therein

An arbitration apparatus using a least recently used (LRU) algorithm, wherein when a plurality of request devices simultaneously request to use a shared resource, such requests are arbitrated in such a manner that the right to use the shared resource is assigned to the request device with the highest priority. The apparatus includes a priority determining unit for receiving shared-resource request signals from a plurality of request devices and resource using order signals respectively associated with the request devices, thereby outputting a grant signal for the request device with the highest priority along with an arbitration-done signal, a recording register for receiving the grant signal, associated with the use of the shared resource, from the priority determining unit, the recording register storing the resource using order based on the grant signal and outputting the stored data to the priority determining unit, and a status machine for receiving the arbitration-done signal from the priority determining unit along with the request signals from the request devices and other control signals, thereby outputting a status information and control signal to the priority determining unit and a recording register control signal to the recording register.

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Kyoungkido, South Korea

Jin Kook Choi