Electronics and Telecommunications Research Institute

Jin Jong Cha

Seong Mo Park

Han Jin Cho

Kyung Soo Kim

An apparatus for motion estimation with control part implemented by state transition diagram without adding delay circuits to processing elements, and capable of maintaining a regular data flow and easily implementing hardware to improve a power consume and speed is disclosed. The apparatus comprises a first and second storage parts for storing data; a measurement part for finding an absolute difference between the data; a step decision part for determining a minimum value; and a control part implemented by state transition diagram.

Apparatus for motion estimation with control part implemented by state transition diagram

An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, includes a first storage device for temporarily storing the run representing the number of zeros ('0's) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulating the output of the second selection circuit based on the feedback signal from a second storage device, the second storage device temporarily storing the output of the accumulator, and an error detector for detecting the errors based on the reference value and the output of the second storage device.

Error detecting circuit in a line length decoding system

A video data run length decoding apparatus is disclosed. The aparatus includes a run length decoder for analyzing a run value of a coded video data, generating a run value, and alternately outputting an interval of a 8-clock signal in which there is a data and another interval of a 8-clock signal in which there is not a data using a gap clock signal, a reverse zig zag and dequantizer for processing a data from the run length decoder based on the reverse zig zag and dequantization operation, and a reverse discrete cosine converter for processing a data outputted from the reverse zig zag and dequantizer, two times, based on the reverse discrete cosine conversion and outputting a two-dimensional video data, thereby decreasing the number of gates of a decoding apparatus and implementing a high speed system by alternately outputting an interval in which there is a data and another interval in which there is not a data using a gap clock signal generator in a run length decoder for a video data run length decoding apparatus.

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Taejon, South Korea

Jin Jong Cha