Semiconductor Manufacturing (shanghai) International Corporation

Semiconductor Manufacturing (beijing) International Corporation

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Jin Jisong

A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, a gate structure being formed on the base, a source/drain doped layer being formed within the base on both sides of the gate structure, and an initial dielectric layer being formed on the base exposed from the gate structure, the initial dielectric layer covering a top of the gate structure, and a source/drain contact plug electrically connected to the source/drain doped layer being formed within the initial dielectric layer on the top of the source/drain doped layer; removing a portion of a thickness of the initial dielectric layer to form a dielectric layer exposing a portion of a side wall of the source/drain contact plug; forming an etch stop layer on at least the side wall of source/drain contact plug exposed from the dielectric layer; etching the dielectric layer on the top of the gate structure using etch stop layers on side walls of adjacent source/drain contact plugs as lateral stop positions, to form a gate contact exposing the top of the gate structure; forming, within the gate contact, a gate contact plug electrically connected to the gate structure. Implementations of the present disclosure facilitate enlargement of a process window for forming a contact over active gate.

Semiconductor structure with gate contact

A semiconductor structure and a forming method thereof are provided. The forming method includes: providing a base, where the base includes a first region; forming a bottom core material layer on the base; forming separate first core layers on the bottom core material layer of the first region; forming a first spacer on a side wall of the first core layer; removing the first core layer; after removing the first core layer, forming a second spacer on a side wall of the first spacer, where the first spacer and the second spacer located on the side wall of the first spacer constitute a main spacer structure layer; patterning the bottom core material layer by using the main spacer structure layer as a masking film to form a second core layer; removing the main spacer structure layer; after removing the main spacer structure layer, forming a third spacer on a side wall of the second core layer; removing the second core layer; and after removing the second core layer, patterning the base by using the third spacer as a masking film to form a desired pattern. Embodiments of the present disclosure can meet the demand of different types of pitches between the desired patterns, and are beneficial to accurately controlling the pitches between the desired patterns.

Semiconductor structure and forming method thereof

A semiconductor structure and a method for forming a semiconductor structure are provided. One form of the method includes: providing a base, a bottom dielectric layer formed on the base, and an interconnecting wire located within the bottom dielectric layer, where the bottom dielectric layer exposes a top of the interconnecting wire; etching a portion of a thickness of the bottom dielectric layer, along an extending direction of the interconnecting wire, where adjacent interconnecting wires and a remainder of the bottom dielectric layer form a groove; forming an etch stop layer at least in the groove, the etch stop layer sealing a top of the groove; forming a top dielectric layer covering the interconnecting wire, the etch stop layer, and the bottom dielectric layer; forming a via within top dielectric layers on both sides of the groove, the via exposing the top of the interconnecting wire; forming a via interconnecting structure filling the via, the via interconnecting structure being electrically connected to the interconnecting wire. Embodiments and implementations of the present disclosure provide reliability and stability of the semiconductor structure while enlarging a process window for forming the via and improving a degree of freedom of a layout design of the via interconnecting structure.

Semiconductor structure and method for forming a semiconductor structure

A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, a dummy gate structure being formed on the base, and a source/drain doped layer being formed within the base on both sides of the dummy gate structure; forming a first dielectric layer on the base exposed from the dummy gate structure, the first dielectric layer exposing a portion of a side wall of the dummy gate structure; forming a self-aligned stop layer on at least the side wall of the dummy gate structure exposed from the first dielectric layer; after the self-aligned stop layer is formed, forming a second dielectric layer on the first dielectric layer, and the second dielectric layer and the first dielectric layer being used as interlayer dielectric layers; after the second dielectric layer is formed, replacing the dummy gate structure with a gate structure; etching the interlayer dielectric layer between self-aligned stop layers on side walls of the adjacent gate structures to form a contact exposing the top of the source/drain doped layer; and forming, within the contact, a contact plug electrically connected to the source/drain doped layer. The present disclosure reduces process difficulty in forming a self-aligned contact plug and simplifies a process flow.

Semiconductor structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. The forming method may include: providing a base; forming, on the base, a to-be-etched material layer, a core material layer located on the to-be-etched material layer, and an HM material layer located on the core material layer; patterning the HM material layer to form HM layers; etching the core material layer between adjacent HM layers, forming a plurality of first grooves exposed from the to-be-etched material layer, and using the remaining core material layer as a core layer; and forming a side wall layer on side walls of the first groove and the HM layer; after the side wall layer is formed, removing the HM layer and the core layer at the bottom of the HM layer, and forming a plurality of second grooves exposed from the to-be-etched material layer; and removing the to-be-etched material layer at the bottom of the first groove and the second groove by using the side wall layer and the remaining core layer as masks, to form a target pattern. In embodiments and implementations of the present disclosure, the pattern precision of the first groove and the second groove is improved. After the target pattern is formed, the pattern precision of the target pattern is correspondingly improved.

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Shanghai, China

Jin Jisong