Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Jin I Hyun

Young Min Kim

Hah Y Yoo

Won Chul Song

An output circuit for a bipolar complementary metal oxide semiconductor. The circuit is formed by coupling P channel and N channel metal oxide semiconductor transistors to bipolar transistors to obtain both a low logic level state of 0 volts and a high logic level state of 5 volts.

Output circuit for a bipolar complementary metal oxide semiconductor

A tri-state logic circuit of a BiCMOS having a power saving characteristic, a strong noise durability, a desirable driving characteristic and switching charaacteristic is disclosed. The circuit comprises PMOS transistors M1,M5 and NMOS transistors M2,M3,M4,M6,M7,M8,M9 and bipolar transistors Q1,Q2 and a capacitor C1.

Growing community of inventors

Yu-Sung, South Korea

Jin I Hyun