Lg Display Co., Ltd.

Jin-Hyung Jung

Sung-Jin Um

Jin-Su Kim

A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate insulating layer on the gate line and the first auxiliary pattern forming a data line in the display region and a second auxiliary pattern in the non-display region over the gate insulating layer, wherein the data line crosses the gate line to define a pixel region forming a passivation layer on the data line and the second auxiliary pattern, and the passivation layer including first and second contact holes respectively exposing the first and second auxiliary patterns forming a planarization layer and a bridge pattern on the passivation layer forming a pixel electrode on the planarization layer and in the pixel region, and a connection pattern on the bridge pattern, wherein the connection pattern contacts the first and second auxiliary patterns.

Array substrate and method of fabricating the same

An array substrate according to an embodiment includes a gate line and a data line in a display region and crossing each other to define a pixel region; first and second auxiliary patterns in a non-display region; a gate insulating layer between the gate and data lines and the first and second auxiliary patterns; a passivation layer on the data line and the second auxiliary pattern and including first and second contact holes respectively exposing the first and second auxiliary patterns; a planarization layer on the passivation layer and including first and second pack holes, which respectively correspond to the first and second contact holes; a bridge pattern between the first and second pack holes and overlapping the second auxiliary pattern; a pixel electrode on the planarization layer and in the pixel region; and a connection pattern on the bridge pattern and contacting the first and second auxiliary patterns.

An array substrate for a liquid crystal display device includes: a gate line and a first storage electrode on a substrate; a gate insulating layer on the gate line and the first storage electrode; a data line over the gate insulating layer, the data line crossing the gate line to define a pixel region; a passivation layer on the data line, wherein a first thickness of the passivation layer and the gate insulating layer over the first storage electrode is thinner than a second thickness of the passivation layer and the gate insulating layer over the gate line; and a pixel electrode and a second storage electrode on the passivation layer, the second storage electrode extended from the pixel electrode and overlapped with the first storage electrode.

Growing community of inventors

Paju-si, South Korea

Jin-Hyung Jung