Samsung Electronics Co., Ltd.

Jin-hyung Cho

Hi-choon Lee

Dong-jin Lee

Byong-mo Moon

An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.

On-die termination circuit, method of controlling the same, and ODT synchronous buffer

A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.

Semiconductor device generating a test voltage for a wafer burn-in test and method thereof

Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.

Semiconductor memory device having local data line pair with delayed precharge voltage application point

A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

Growing community of inventors

Suwon-si, South Korea

Jin-hyung Cho