Samsung Electronics Co., Ltd.

Jin-hyun Kim

Won-hyung Song

Oh-seong Kwon

Hyun-Ho Choi

A memory module includes a first memory device configured to receive data and first information from a hardware accelerator, to generate an arithmetic result by performing arithmetic processing using the data and the first information, and to output the arithmetic result through an interface with at least one other memory device; and a second memory device configured to receive the arithmetic result from the first memory device through the interface without using the hardware accelerator, and to store the arithmetic result.

Memory device performing parallel arithmetic processing and memory module including the same

Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a memory cell array; a standard cell region in which first type standard cells implemented to perform a first operation for accessing the memory cell array and second type standard cells performing the first operation and having performance characteristics different from performance characteristics of the first type standard cells are arranged; and a ROM including a program that performs place and route for the standard cells arranged in the standard cell region.

Integrated circuit memory devices with customizable standard cell logic

A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells. The first interface circuit is configured to receive a DRAM interface signals, and the second interface circuit is configured to receive a flash memory interface signals.

Multi-port semiconductor memory device with multi-interface

A non-volatile memory device uses division addressing scheme and N address input terminals. A address decoder of the non-volatile memory device simultaneously activates a row select signal and a column select signal by synchronizing a first N-bit address signal and a second N-bit address signal sequentially input after the first N-bit address signal.

Non-volatile memory device using division addressing and electronic device including same

A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current.

Resistive memory device and method of writing data using multi-mode switching current

A low voltage differential signal driver includes first and second current sources, a first branch and a second branch. The first branch includes at least two transistors and at least two resistors between them that are all connected in series between the first and second current sources, to define a first node between adjacent resistors that is configured to transmit and receive differential signals. The second branch also includes at least two transistors and at least two resistors between them that also are all connected in series between the first and second current sources, to define a second node between adjacent resistors that is also configured to transmit and receive differential signals.

Low voltage differential signaling drivers including branches with series resistors

A shift register including an electrical fuse and a method of operating the shift register are disclosed. The shift register includes a register flip-flop group circuit and a plurality of output circuits respectively receiving a plurality of enable signals. Each output circuit includes a fuse control flip-flop receiving one of the plurality of enable signals and outputting a fuse control signal in response to the one enable signal. Each output circuit also includes an electrical fuse receiving the fuse control signal and outputting an electrical fuse mode signal, and a multiplexer outputting either the register output signal or the electrical fuse mode signal as a final output signal in accordance with the one enable signal.

Shift register comprising electrical fuse and related method

We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.

voltage level coding system and method

Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a control circuit. The pre-driver unit modifies a common mode level and the amplitude of first internal output signals to generate internal output signals in response to driver control signals. The main driver unit modifies the common mode level and the amplitude of the second internal output signals. The control circuit detects the common mode level and the amplitude of a connected circuit. The common mode level and the amplitude of the output signals may then automatically be adjusted to be the same as the common mode level and the amplitude of this connected circuit High speed signal conditioning may be accomplished.

Transmitter of a semiconductor device

An input buffer includes a control circuit that generates first control signals depending on a signal type of at least one input signal. The input buffer also includes a receiver that generates at least one output signal of a predetermined signal type from the at least one input signal and the first control signals. Thus, for a semiconductor device using a plurality of such input buffers, interface circuits of application circuits communicating with the semiconductor device are eliminated, thereby minimizing power consumption and layout area.

Input buffer and semiconductor device including the same

A receiving device which may include a plurality of pre-amplifiers and a plurality of samplers. Each of the plurality of samplers is connected to the output ports of a corresponding pre-amplifier. Each sampler samples data signals input thereto in response to a corresponding clock signal. The receiving device of a semiconductor memory unit may reduce input capacitance seen from the outside of chip and eliminate mutual interference of signals so as to prevent errors from being generated when data is extracted in the event of over sampling using pre-amplifiers. Furthermore, the receiving device can separately control the pre-amplifier for samplers that receive clock signals for data alignment and the pre-amplifier for samplers that accept clock signals for repeated data reception.

Input signal receiving device of semiconductor memory unit

A data driving circuit includes a driver in which a driving current is controlled in response to predetermined bits of digital control signal and which receives a differential input data signal to generate differential output data signal; and a digital control signal generator for storing and generating the digital control signal. The driver includes a pre-driver for passing a pre driving current in response to a bias voltage and for receiving the differential input data signal(s) to generate first and second signals; and a main driver in which a main driving current is controlled in response to the digital control signal and which generates the differential output data signals in response to the first and second signals. The data driving circuit can not only vary an amplitude and a level but also shift a level, and by varying a current of the current sources in response to the digital control signal, a margin is secured in a saturation region of transistors which constitute the current sources, thereby generating a stable differential output data signals insensitive to a noise.

Data driving circuit and semiconductor memory device having the same

A print head of an ink-jet printer including a main chip area having at least one ink jetting portion disposed on a substrate to jet ink, and at least one bonding pad connected with a corresponding lead end of a wiring of a circuit part to control the ink jetting portion; and a scribe lane area disposed around the main chip area and forming a cutting region in which the main chip area is divided from main chip areas of other print heads by cutting, the scribe lane area having a damping pattern portion formed to be electrically and physically isolated from the main chip area and the substrate.

Print head of an ink-jet printer and fabrication method thereof

An ink-jet printhead and a method of manufacturing the same includes a substrate in which a manifold supplying ink is formed, a nozzle plate which is formed to be spaced-apart from the substrate by a predetermined gap and in which a nozzle through which ink is ejected is formed, a barrier wall which seals a space formed between the substrate and the nozzle plate to define an ink chamber filled with the ink to be ejected, an ink channel connected to the ink chamber, and an ink feed hole connecting the ink channel to the manifold, and an insulating layer which is formed on the substrate to form lower walls of the ink chamber, the ink channel, and the ink feed hole, where a heater generating bubbles by heating the ink filled in the ink chamber is formed on the lower walls of the ink chamber. The ink feed hole includes a plurality of through holes which perforate the insulating layer and through which the ink channel is connected to the manifold, and a plurality of posts which are formed on the insulating layer and support the nozzle plate.

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Yongin-si, South Korea

Jin-hyun Kim