Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Jin-Hyo Lee

Kyu-Hong Lee

Dae-Yong Kim

Sang-Hoon Chai

Won-Gu Kang

Jong-Sun Lyu

The present invention relates to a pillar bipolar transistor and the fabricating method thereof, the active region on which the emitter region, the base region and the collector region are formed, is defined at the first pillar by the trench formed in the semiconductor substrate, a party of the base region and the polysilicon base electrode is electrically connected by the base connection, thereby decreasing the contact area and protecting to increase the extrinsic region of the base, and protecting to mask a juction of base to emitter at high concentration. Also, the polysilicon emitter electrode having the wide surface area is formed by self-aligned contact using the CMP method on the upper of the emitter region. Therefore, the active region of the transistor is defined in the first pillar, so that the parasitic capacitance between the emitter and the collector, and the base is decreased, and the contact area between the base region and the polysilicon base electrode is also decreased, thereby enhancing the operational characteristic of the transistor by protecting to increase the extrinsic region of the base, and the current gain similar to the forward operation of the transistor can be obtained in the backward operation of the transistor. Also, the emitter polysilicon electrode having the wide surface is self-arranged with the emitter region, thereby easily forming the contact opening to form the emitter electrode.

Pillar bipolar transistor

A bipolar transistor and a process for manufacturing thereof is disclosed. The bipolar transistor has a self-aligned base electrode in which first and second pillars are formed within first and second trenches which act as an activated region and a collector region, respectively; a conductive impurities layer of high density formed at a bottom side of the first and second trenches and at a lower portion of an isolation wall between the first and second trenches; and a sequentially formed base and emitter layer. After connection to the base layer, a base contact electrode is formed within the first trench, and a collector contact electrode is formed by implanting second conductive impurities in the second pillar.

Bipolar transistor having a self-aligned base electrode and method for

Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed upward the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base at a center portion thereof; injecting an impurity to form an emitter at an upper portion of the first pillar; depositing a third polysilicon layer on the emitter, the third polysilicon layer being formed wider than the emitter; and forming self-aligned contact holes to form electrodes through the contact holes.

Method for fabricating pillar bipolar transistor

A dynamic random access memory (DRAM) with low noise characteristics comprises a plurality of memory cells each consisting of a pair of reference memory cells respectively arranged between a word line and a pair of adjacent bit lines. The reference memory cells store signals of opposite levels corresponding to one bit of information. Each of the reference memory cells consists of a capacitor and switching transistor. One end of the capacitor is connected to the collector of the transistor. The other end of the capacitor is connected to one of the pair of bit lines adjacent thereto. The base of the transistor is connected to the word line, and the emitter of the transistor is completed to receive a reference voltage.

Dynamic random access memory with low noise characteristics

A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Vertically stacked bipolar dynamic random access memory

A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.

Growing community of inventors

Daejeon, South Korea

Jin-Hyo Lee