Dongbu Electronics, Co. Ltd.

Db Hitek Co., Ltd.

Dongbu Hitek Co., Ltd.

Dongbu Anam Semiconductor, Inc.

Jin Hyo Jung

Sang Yong Lee

Jung Hyun Lee

Dong Hoon Park

Hae Taek Kim

Hyun Joong Lee

Seung Ha Lee

Ja Geon Koo

Bum Seok Kim

Dae Il Kim

Seung Hyun Eom

Ki Won Lim

Hyun Jin Kim

Young Jin Kim

Sang Bum Lee

Sung Do Kwon

Chang Hee Kim

Sang Gil Kim

Seung Ki Ko

Ki Hun Lee

Tae Ryoong Park

Kyong Rok Kim

Jung Ah Kim

Min Kyung Ko

Provided is an RF switch device and a method of manufacturing the same and, more particularly, to an RF switch device that improves the on-resistance (Ron) of the RF switch by including an integral or integrally formed P diode. The RF switch device includes a first active region on a first substrate as a first base, a second active region on the first substrate spaced apart from the first active region as a second base, and a gate electrode on the first active region and on the second active region.

RF switch device

An RF switch device in a stacked configuration and a method of manufacturing the same seek to reduce or eliminate a voltage imbalance, a condition in which different voltages are applied to different stages of the RF switch device, by forming air gaps on or over corresponding gate electrodes, in which each of the air gaps in a single stage has a different width.

RF switch device including multi-width air gaps

Disclosed is an RF switch device and, more particularly, an RF switch device having an air gap over a gate electrode and a metal interconnect at a position higher than the air gap and that at least partially overlap the air gap in the vertical direction, thereby preventing exposure of an upper portion of the air gap in subsequent processing.

An RF switch device and a method of manufacturing the same are proposed. A trap area is formed in or on a surface of a highly resistive substrate to trap carriers accumulating on the surface of the substrate, thus improving RF characteristics.

RF switch device having a highly resistive substrate, an isolation layer therein or thereon, and a trap-rich layer therein or thereon

A semiconductor device is disclosed. The semiconductor device includes impurity regions formed in surface portions of a substrate, gate structures formed on surface portions of the substrate between the impurity regions, a first insulating layer formed on the impurity regions and the gate structures, first wiring patterns formed on the first insulating layer, and first contact patterns connecting the impurity regions and the first wiring patterns through the first insulating layer, and the first wiring patterns are arranged in a zigzag shape.

Semiconductor device formed on SOI substrate

A signal control unit for an organic light emitting diode (OLED) display device includes a substrate structure including a plurality of active elements for the pixels, first metal electrodes disposed on the substrate structure, and configured to be electrically connected to a portion of each of the active elements, second metal electrodes disposed over and adjacent the first metal electrodes, configured to electrically connected to corresponding ones of the first metal electrodes, respectively, by via contacts extending vertically to electrically connect the first metal electrodes to the second metal electrodes, and interlayer insulating layer structure interposed between the first electrodes and the second electrodes and having the via contacts therein, the interlayer insulating layer structure having a stacked structure in which a first interlayer insulating layer, a light blocking layer and a second interlayer insulating layer are stacked in order.

Signal control unit for an organic light emitting diode display device

A signal control unit for an organic light emitting diode (OLED) display device, includes a substrate structure including a plurality of active elements each corresponding to a pixel, a lower metal pattern disposed on the substrate structure, and electrically connected to a portion of the plurality of active elements, an insulating interlayer disposed on the substrate structure and at least partially covering the lower metal pattern, a via contact penetrating through the insulating interlayer and connected to the lower metal pattern, a metal electrode disposed on the insulating interlayer, and connected to the via contact, and an electrode passivation layer pattern substantially covering the metal electrode to expose a center portion of an upper surface of the metal electrode while covering a remainder of the upper surface and a side surface of the metal electrode. Therefore, leakage current which flows through the side surface of the metal electrode is suppressed.

Signal control unit for an organic light emitting diode display device, method of manufacturing the same, and organic light emitting diode display device including the same

An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.

Element isolation layer structure and method of manufacturing the same

In embodiments, a high voltage semiconductor device includes a gate structure disposed on a substrate, a source region disposed at a surface portion of the substrate adjacent to one side of the gate structure, a drift region disposed at a surface portion of the substrate adjacent to another side of the gate structure, a drain region disposed at a surface portion of the drift region spaced from the gate structure, and an electrode structure disposed on the drift region to generate a vertical electric field between the gate structure and the drain region.

High voltage semiconductor device and method of manufacturing the same

Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide layer in the first trench; a third oxide layer on the semiconductor substrate and on inner surfaces of the second and third trenches; and a polysilicon layer on the third oxide layer to fill the second and third trenches.

Capacitor for semiconductor device and manufacturing method of capacitor for semiconductor device

A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at one side of the first gate and a second conductive type second ion implantation region disposed in the first conductive type well at the other side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at one side of the second gate and a first conductive type second ion implantation region disposed in the second conductive type well at the other side of the second gate; and a line electrically connecting the second conductive type second ion implantation region with the first conductive type first ion implantation region.

Semiconductor memory device and method of manufacturing the same

A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate.

Flash memory device and programming and erasing methods therewith

Semiconductor devices and a fabricating method therefore are disclosed. One method includes forming a buffer oxide layer and a buffer nitride layer on the top surface of a semiconductor substrate; forming a photoresist pattern on the pad nitride layer and forming a trench by etching the buffer nitride layer, the buffer oxide layer and the semiconductor substrate by a predetermined etch using the photoresist pattern as a mask; forming sidewall floating gates on the lateral faces of the trench; depositing polysilicon on the entire surface of the resulting structure; forming a gate electrode by patterning the polysilicon of the resulting structure; removing the buffer nitride layer and forming a poly oxide layer on the exposed part of the polysilicon of the gate electrode; forming source/drain regions by implanting impurities into the predetermined part of the resulting structure; injecting electric charges into the sidewall floating gates; and forming spacers on the lateral faces of the sidewall floating gates and the gate electrode.

Semiconductor device and fabricating method thereof

A method and non-volatile memory device are provided that are characterized by ion-implantation of impurities in the sidewalls of a first electrode. The inclusion of impurities in the sidewalls eliminates geometric abnormalities, referred to herein as a bird's beak, in the first electrode, which are caused by numerous oxidation processes being performed in the overall memory fabrication process. By eliminating these geometric abnormalities, thickening of the block oxide layer proximate the area of geometric abnormalities does not occurring, resulting in a memory device capable of efficiently programming and erasing data.

Non-volatile memory device and method for fabricating the same

A flash memory and a flash memory fabrication method for increasing the coupling ratio by HSG including forming a STI region on a silicon substrate to define an active region, forming a tunneling oxide layer on the active region, and depositing an amorphous silicon layer on the silicon substrate. The method also includes patterning the amorphous silicon layer along a bit line direction, forming an embossed silicon layer including HSGs on the patterned amorphous silicon layer, and sequentially depositing an ONO layer and a polysilicon layer for a control gate on the resulting structure. The method further includes forming a photoresist pattern on the polysilicon layer, and forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along the bit line.

Growing community of inventors

Bucheon-si, South Korea

Jin Hyo Jung