Samsung Electronics Co., Ltd.

Sungkyunkwan University

Research and Business Foundation Sungky

Jin-Hong Park

Sungjun Kim

Sungjoo Lee

Jeong-Ho Yeo

Keun Heo

Kilsu Jung

Jin Su Park

Sang-Yong Park

Sunghun Lee

In-Sung Kim

Jeong-Hoon Lee

Sang Ki Nam

Keun Hang Heo

Dae-youp Lee

Jin-seok Heo

Doo-Hoon Goo

Chang-Min Park

Joo-On Park

Kyu-hee Han

Jae-Woong Choi

Maksim Andreev

Jin-ok Kim

Gwang-we Yoo

Sungpyo Baek

Jae Hyeok Ju

Jingyuan Jia

Kwan-Ho Kim

Sumin Jeon

A photodetector includes a gate electrode extending in a first direction, a ferroelectric layer on the gate electrode and maintaining a state of polarization formed by a gate voltage applied to the gate electrode, a light absorbing layer on the ferroelectric layer and extending in a second direction intersecting the gate electrode, the light absorbing layer including a two-dimensional (2D) material of a layered structure, a source electrode on the ferroelectric layer and connected to a first end of the light absorbing layer, and a drain electrode on the ferroelectric layer and connected to the a second end of the light absorbing layer.

Photodetector and image sensor including the same

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

Negative differential resistance device

A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

Semiconductor memory device using a ferroelectric characteristic of charge storage layer and operating method thereof

A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Three-dimensional semiconductor integrated circuit

A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip. Therefore, effects of low power consumption, a reduced size, and high speed of a chip may be achieved.

Multi-negative differential transconductance device and method of producing the same

A method of manufacturing an integrated circuit (IC) device includes exposing a partial region of a photoresist film formed on a main surface of a substrate to generate acid, and diffusing the acid in the partial region of the photoresist film. Diffusing the acid may include applying an electric field, in a direction perpendicular to a direction in which the main surface of the substrate extends, to the photoresist film using an electrode facing the substrate through an electric-field transmission layer filling between the photoresist film and the electrode. The electric-field transmission layer may include an ion-containing layer or a conductive polymer layer.

Method of manufacturing integrated circuit device

The present disclosure provides a multi-functional electronic device with a black phosphorous-based single channel, wherein the device comprises: a black phosphorous-based single channel layer including a horizontal arrangement of a first semiconductor region and a second semiconductor region to define a horizontal junction therebetween, wherein the second semiconductor region has a lower hole-carrier density than the first semiconductor region; a first electrode connected to the first semiconductor region; a second electrode spaced from the first electrode and connected to the second semiconductor region; an ionic gel layer disposed on the first semiconductor region; and a gate electrode for receiving a gate voltage to generate an electric field in the channel layer.

Electronic device based on black phosphorous single channel with multi-function and method of manufacturing the same

A method of detecting reticle error may include using an optical source of an exposure unit to cause light to be incident on a reticle installed in the exposure unit, and detecting the reticle error using only 0diffraction light from among diffraction lights transmitted through the reticle. A method of detecting reticle error may include: installing a reticle, including a mask substrate and mask patterns having a critical dimension formed on the mask substrate, in an exposure unit to cause light to be incident on the reticle; exposing a photoresist film disposed on a wafer in the exposure unit using only 0diffraction light from among diffraction lights transmitted through the reticle; developing the exposed photoresist film; and analyzing a thickness change, an image, or the thickness change and image of the developed photoresist film, in order to detect the reticle error at a wafer level.

Method of detecting reticle errors

In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at least one portion of the first surface of the template includes a photo attenuation member. A light is irradiated onto the photocurable coating layer through the template to form a cured coating layer including second patterns having a second dispersion degree of sizes. The second patterns are generated from the first patterns and the second dispersion degree is less than the first dispersion degree. The template is separate from the cured coating layer. A size dispersion degree of the patterns used in a nanoimprint lithography process may be adjusted by the light attenuation member, so that the fine patterns may be formed to have an improved size dispersion degree.

Methods of forming fine patterns using a nanoimprint lithography

Growing community of inventors

Hwaseong-si, South Korea

Jin-Hong Park