Samsung Electronics Co., Ltd.

Jin-hong Oh

Sun-young Shin

Kyung-ah Jeong

Kyung-Koo Lee

A system on a chip may include a codec module configured to receive an image including a plurality of first pixel data and output a plurality of second pixel data through a system bus. The codec module comprises at least one (M+N) bit logic circuit including M bit logic and N bit logic. The codec module is configured to operate in a first mode where the (M+N) bit logic circuit performs a dithering operation on the first pixel data of (M+N) bits and generates the second pixel data including at least M bits. The codec module is configured to operate in a second mode where the M-bit logic selectively operates and outputs the second pixel data of M bits.

Image processing device, image processing system including image processing device, system-on-chip including image processing system, and method of operating image processing system

An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

Image processor, image processing system including image processor, system-on-chip including image processing system, and method of operating image processing system

A method of processing image data comprises processing a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

An image processor processes a plurality of pixels. Each of the pixels include a first and second set of bits that can be separately or simultaneously in first and second regions of a memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may be selected according to the width of a used data bus and/or features of a peripheral device connected to the image processor such as a display.

A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.

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Hwaseong-si, South Korea

Jin-hong Oh