Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Jin-Hong Ahn

Tae-Hyoung Kim

Joong-ho Choi

Joo-Hiuk Son

Boo Yong Park

Oh-Sang Yoon

Hae-Young Rha

Jeong-Su Jeong

Sung-Ho Wang

A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which is delayed by an input buffer, respectively, a time interval extraction chain extracting a time interval between a rising edge of the input clock signal and a rising edge of the delay clock signal in accordance with clock signals multiplied in the first and second toggle flip-flops, and a variable delay chain delaying the input clock signal by a time interval extracted from the time interval extraction chain. The circuit employs a &frac12; multiplied clock signal and operates without regard to a duty cycle of an input clock signal, thereby compensating for all the delay time within the cycle of the input clock signal.

Delay time compensation circuit for clock buffer

A circuit for reading data from a memory device reduces electric power consumption by recycling in a precharge period the charge consumed in a preceding sensing period. The circuit includes a pair of data lines set to a voltage level higher than a precharge voltage by the sensing operation of a pull-up amplifier, and a pair of data lines set to a voltage level lower than the precharge voltage by the sensing operation of a pull-down amplifier. The charge consumed in the sensing period is recycled by electrically connecting the two pairs of data lines, respectively, during a succeeding precharge period.

Sensing circuit with charge recycling

An address signal transition detecting apparatus includes an address transition detecting circuit for detecting transitions in address signals, accordingly generating address transition detection signals and summing the address transition detection signals to generate an address transition detection sum signal ATDSUM, respectively outputting a first pulse signal YE for activating a column address decoder, a second pulse signal P for activating a precharger and a third pulse signal SE for activating a sense amplifier in accordance with an address transition detecting sum signal ATDSUM, and once again outputting another first pulse signal YE for activating the column address decoder in response to a fourth pulse signal YE2 generated in accordance with the address transition detection sum signal ATDSUM and the first pulse signal YE. The apparatus enables accurately reading a data signal on a data line by twice generating the first pulse signal YE that serves to activate the column address decoder, whereby the sense amplifier is able to sense a data signal in an improved manner.

Address signal transition detecting circuit for semiconductor memory

An improved cell array and sense amplifier structure and embodied method are disclosed. The structure exhibits an improved noise characteristic by decreasing a coupling noise which occurs between bit lines by using, as a reference bit line, a bit line from an array of memory cells other than the array to which the bit line belongs, thus forming a predetermined spacing between a bit line and a reference bit line. The structure includes: an upper sense amplifier having an input terminal commonly connected with a first pair of bit lines of an adjacent first cell array and another input terminal commonly connected with a first pair of bit lines of a non-adjacent second cell array; and a lower sense amplifier having an input terminal commonly connected with a second pair of bit lines of the second cell array and another input terminal connected with a second pair of bit lines of the first cell array.

Cell array and sense amplifier structure exhibiting improved noise

A hierarchical word line structure for a semiconductor memory is provided that substantially eliminates coupling noise between neighboring wiring lines by driving neighboring sub-word lines by different main word lines. The hierarchical word line structure further reduces a layout size. The hierarchical word line structure uses one less transistor than a related art sub-word line driver. The word line includes a plurality of word line rows that each include a plurality of sub-word line drivers. The sub-word line drivers receive sub-word line driver enable signals among which only one signal becomes high level at a time. Each of the word line rows correspond to a main word line and a subset of the plurality of sub-word line drivers that drive neighboring sub-word lines are coupled to different respective main word lines.

Hierarchical word line structure

A memory device has a page copy mode that writes data into memory cell by memory page units by using a common bit line without outputting accessed data externally. The memory device, e.g., a DRAM includes an interface unit having an address multiplexor for multiplexing a plurality of address signal bits in accordance with a row address strobe signal. A row address resetting unit is for resetting an output signal from the address multiplexor in accordance with the row address strobe signal. A pre-decoder decodes an output signal from the row address resetting unit. A row decoder is for decoding an output signal from the pre-decoder. A word line driving unit receives an output signal from the row decoder to drive a corresponding word line. A block decoding signal latch unit latches an output signal from the pre-decoder in accordance with a page copy signal. A block decoder decodes an output signal from the block decoding signal latch unit and a sense amplifier controller receives an output signal from the block decoder. The sense amplifier controller outputs a sense amplifier enabling signal and a sense amplifier equalizing signal to a sense amplifier driving unit.

Memory device having page copy mode

A bit line structure is disclosed. Which includes: sense amplifiers each connected to two pairs of bit lines BL and /BL through bit line selecting switches, to the bit line a plurality of cells are connected, includes: a first bit line pair BL and /BL and a second bit line pair BL and /BL formed by dividing a bit line disposed within a same column respectively in a cell array; a first connecting bit line for connecting the bit line BL of said second bit line pair to said sense amplifier; a second connecting bit line for connecting the bit line /BL of said second bit line pair to said sense amplifier; said second connecting bit line having two crossing sections 25 crossing with another second connecting bit line for connecting a bit line BL of a second bit line belonging to an adjacent sense amplifier; and bit line selecting switches for connecting said first bit line pair and said second bit line pair respectively to said sense amplifier, whereby a number of memory cells connected to each bit line is reduced to 1/2 compared with the conventional technique, the bit lines are arranged 3-dimensionally to eliminate the area loss in carrying out the layout, and particularly, the connecting bit lines are made of a conductive material which has a smaller resistance than a conductive material of the bit lines.

Bit line structure with bit line pass over configuration

Bit line structure

A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections. According to the present invention, the bit line selecting signals operate in such a manner that: during a bit line selection, a bit line selecting signal for connecting one pair of bit lines among the n pairs of bit lines to the sense amplifier is made to have a voltage level capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section without a voltage loss; the other bit line selecting signals corresponding to the non-selected remaining bit lines are given a voltage incapable of connecting the bit lines the sense amplifier by the bit line selecting section; thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section; and the bit line selecting signals which do not correspond to the bit line selected just before are maintained without a voltage shifting.

Growing community of inventors

Kyungki-Do, South Korea

Jin-Hong Ahn