Samsung Electronics Co., Ltd.

Skhynix Inc.

Jin-Ho Oh

Jeong-Hee Park

Su-Hyun Lee

Jong-Seok Kim

Soon-Oh Park

Ki-hong Kim

Jung-hwan Park

Jin-Ho Bin

Il-Young Kwon

Tae-Hong Gwon

Cheon-Oh Lee

Nam-Hyun Kim

Mi-Jeong Song

Hun-Joo Lee

Yeon-Jeong Kim

A method for fabricating the three dimensional (3D), non-volatile memory (NVM) device includes: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of first material layers which are alternately stacked; forming at least one channel hole penetrating through the stack structure; forming a second material layer along the at least one channel hole; trimming a surface of the second material layer; oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer; and forming a charge storage layer and a tunnel insulating layer over the charge blocking layer.

Non-volatile memory device and method for fabricating the same

A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

Method of forming a phase change material layer pattern and method of manufacturing a phase change memory device

A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation.

Short pulse rejection circuit and method thereof

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Gyeonggi-do, South Korea

Jin-Ho Oh