Skhynix Inc.

Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Osong Medical Innovation Foundation, Korea University Research and Business Foundation

Jin Ho Jeong

Dae Suk Kim

Mun Seon Jang

Munseon Jang

Ho Seok Son

Jin Bo Shim

Myoung-Ho Kwon

Jong Sun Park

Sang-Jin Lee

Saeng Hwan Kim

Hoiju Chung

Kyung Whan Kim

Won Gyu Shin

Myoung Keun Kwon

A Ram Rim

Gyu Sik Lim

Dong Yeob Shin

Sang Woo Yoon

Jung Hak Lee

Min Jae Lee

Hong Man Chang

Kwan Ho Bae

Mee Ran Cho

Hyun Shik Shin

Yeon Hee Kook

Seung Hwan Bang

A dynamic fault clustering method and apparatus for efficiently managing redundancy in semiconductor memories performs a collection operation of searching for and detecting a fault and an operation of appropriately clustering the fault at the same time, which reduces an amount of time spent performing Built-In Redundancy Analysis (BIRA).

Dynamic fault clustering method and apparatus

An electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. The electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.

Electronic system for monitoring error of address

A memory device includes a memory cell area including a plurality of cell blocks divided into a plurality of normal cell blocks, at least one ECC cell block, and at least one redundancy cell block, the plurality of cell blocks being configured to output data and error correction codes; an error correction circuit configured to generate error-corrected data by correcting errors in the data using the error correction codes; a first switch group configured to output the error-corrected data while performing, according to first repair control information, a shifting operation on the error-corrected data; and a second switch group configured to transfer the data from the memory cell area to the error correction circuit while performing, according to second repair control information, a zero-padding operation on the data output from one of the cell blocks.

Memory device including error correction device

A semiconductor module includes an address control circuit configured to generate an internal address based on an address in a first read operation and a second read operation that are sequentially performed and configured to generate multiple decoding enable signals and an error information enable signal, a memory circuit including multiple mats and configured to output internal data based on the internal address and the multiple decoding enable signals in the first read operation and configured to output internal meta data and second internal parities based on the internal address and the multiple decoding enable signals in the second read operation, and an error information storage circuit configured to output first internal parities based on the internal address and the error information enable signal in the first read operation.

Semiconductor module for performing error correction operation

A memory includes a first check matrix calculation circuit configured to generate a first parity based on a group indicator portion of a check matrix and write data; a memory core including cell regions configured to store therein the write data and the first parity, neighboring ones of the cell regions sharing one or more sub-word line drivers; a first syndrome calculation circuit configured to generate a first syndrome based on the first parity read from the memory core and a first result of calculating the group indicator portion and data read from the memory core; and a failure determination circuit configured to detect, for each row of the memory core, a defective one of the sub-word line drivers based on the first syndrome.

Memory and operation method of memory

Disclosed is an operating method of a memory, and the operating method may include reading, from selected memory cells included in the memory, codewords including data and an error correction code; detecting errors in the codewords; correcting the errors in the codewords; re-writing the error-corrected codewords to the selected memory cells; re-reading the re-written error-corrected codewords from the selected memory cells; and determining whether the errors are permanent errors in response to a determination that an error is present in the re-read error-corrected codewords.

Memory including error correction circuit and operating method thereof

A display device includes a first display area including a first pixel area; a second display area including a second pixel area and a transmissive area; a signal line, a common electrode, and a touch electrode that are disposed in the second display area. The common electrode includes an opening overlapping the transmissive area, and the common electrode is disposed between the signal line and the touch electrode to overlap the signal line.

Display device

An error processing circuit includes: a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation; a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation; and a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation.

Error processing circuit, memory and operation method of the memory

A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.

A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.

Reed-Solomon code soft-decision decoding method and device

Disclosed is a cooking apparatus for providing a cooking vessel suitable for a simmer cooking function. A cooking apparatus of the present invention includes a cooking room; a cooking vessel accommodated in the cooking room, and including a main body, and a heating element attached on a bottom of the main body and configured to be heated by microwaves to heat the main body; a microwave heater configured to radiate microwaves to the cooking vessel; an input device configured to receive a simmer cooking command; and a controller configured to repeatedly perform a process of turning on the microwave heater for a first time period, when the simmer cooking command is received through the input device, and turning off the microwave heater for a second time period when the first time period elapses, for a cooking time period, and configured to perform a keeping-warm process when a door does not open in a third time period after the cooking time period elapses.

Cooking apparatus

An oven with an enhanced structure to improve cooking performance is provided. The oven includes a main body, a cooking chamber arranged inside the main body, the cooking chamber including an open front, a door arranged to open or close the front of the cooking chamber, a circulation fan arranged to circulate air in the cooking chamber, a suction port formed on a wall of the cooking chamber facing the circulation fan, a turn table arranged on a bottom plate of the cooking chamber, the turn table being rotatable around a rotating shaft, and a discharging port formed on the bottom plate of the cooking chamber, the discharging port for discharging air that has passed through the suction port into the cooking chamber, the discharging port being located under the turn table.

Growing community of inventors

Seoul, South Korea

Jin Ho Jeong