Electronics and Telecommunications Research Institute

Jin Ho Hahm

Young Sun Kim

Jun Hwa Lee

Sang Wan Kim

Sung Min Kim

Kyeong Ho Lee

Dong Won Kang

Joon Kyung Lee

Sang Sik Yoon

Sang Kil Park

Kyung Pyo Jun

Wang Bong Lee

Taesang Choi

Woo Seop Rhee

Sang Ha Kim

Sang Joong Kim

Mi Jung Yang

Young Boem Choi

Ki Dong Nam

An apparatus for virtualizing network equipment provides at least one virtualized network equipment by virtualizing the network equipment, schedules the pieces of virtualized network equipment, and executes a relevant program. Here, the virtualization apparatus performs context switching according to the scheduling in the time unit of context switching and switches to another program.

Apparatus and method for virtualizing of network device

A traffic control apparatus is provided which includes an interface connector to transmit/receive an Internet Protocol (IP) packet to/from an external circuit, a frame generator to receive the IP packet through the interface connector and to generate a Media Access Control (MAC) frame, and a network processor to transmit/receive the IP packet to/from the frame generator, to execute at least one programmable application, and to identify and classify the at least one programmable application.

Apparatus and method for controlling traffic

In the adaptive connection admission control method of the present invention, a corresponding ingress edge node performs connection admission control for a new connection within the amount of bandwidth initially allocated to each of paths between the ingress and egress edge nodes. The amount of remaining bandwidth allocated to a specific path Pr is compared with an amount of bandwidth required for a call requesting new connection setup input to the corresponding ingress edge node. The amount of additional bandwidth to be requested from the bandwidth broker is predicted when the amount of the remaining bandwidth does not satisfy the amount of bandwidth required for the connection setup requesting call. The ingress edge node requests additional bandwidth from the bandwidth broker on the basis of the predicted amount of the additional bandwidth, changing bandwidth information of the corresponding path Pr, and performing connection admission control.

Method of performing adaptive connection admission control in consideration of input call states in differentiated service network

The system of the present invention guarantees quality of service with respect to packets transmitted/received between an external network capable of providing differentiated services and a home network. The system includes a packet classifier, a marker, a priority class queue, a scheduler and a token bucket. The packet classifier classifies the packets according to addresses and traffic types. The marker allocates information on priorities to packets transmitted from the home network to the external network. The priority class queue has a plurality of queues classified according to the priorities. The scheduler services packets stored in the priority class queue according to the priorities. The token bucket drops packets, bandwidths of which are above a preset maximum bandwidth, when the packets are generated.

System and method for guaranteeing quality of service in IP networks

The present invention relates to a memory interface controller for a data transmission system. A memory interface controller is capable of randomly accessing a memory using an associative memory and variably processing data using an extended memory. There is provided a memory interface controller which includes a control logic unit for selectively outputting signals; a comparand register for storing a sequence number; an associative memory for outputting a match address; a priority address encoder for outputting a priority match address; an external memory controller for outputting an empty address of the associative memory; an external tended memory controller for outputting a priority empty address; and an extended memory address and control signal generator for generating an address and a control signal (enable/read/write).

Memory interface controller

A memory device having unmultiplexed address inputs for performing an address control function including an address control input (AC) port, address inputs and an address arithmetic unit which performs the address control function by summing up these inputs. These units are connected such that the summed address of the address inputs and the address control input is applied to the memory as the actual address. Also provided is a memory device having multiplexed address inputs for performing an address control function including an address control input (AC) port, a row address select input (RAS) port, and an address arithmetic unit for performing an address control function by controlling these ports. The ports are connected such that, when considering the address actually applied from the multiplexed address input, the address control input (AC), and the row address select input (RAS), if the RAS signal was applied, the sum of the row address select input and the address control input (AC) is applied to the memory as the actual lower address, and if the column address select input (CAS) was applied, the sum of the address input and the carry produced by lower address is applied to the memory as the actual upper address.

Memory device having address control function

Growing community of inventors

Daejeon, South Korea

Jin Ho Hahm