Skhynix Inc.

Micron Technology Incorporated

Jin Ho Bin

Ki Hong Lee

Seung Ho Pyi

Il Young Kwon

Soo Jin Kim

Il Do Kim

Ii Young Kwon

Hye Hyeon Byeon

A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

Semiconductor device and manufacturing method thereof

A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.

Method of forming thin layers and method of manufacturing a non-volatile memory device using the same

A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Three-dimensional structured memory devices

A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.

Semiconductor device

A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.

Semiconductor device having three-dimensional structure and method of manufacturing the same

A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.

Transistor, semiconductor device and method of manufacturing the same

A semiconductor device includes a pipe gate, word lines stacked on the pipe gate, first channel layers configured to pass through the word lines, and a second channel layer formed in the pipe gate to connect the first channel layers and having a higher impurity concentration than the first channel layers.

Semiconductor device and method of manufacturing the same

A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.

Growing community of inventors

Seoul, South Korea

Jin Ho Bin