Samsung Electronics Co., Ltd.

Skycross, Inc.

Other

Jin Hee Yoon

Young-Min Jo

John Charles Farrar

Gregory A O'Neill, Jr

Se-Hyun Oh

Murray Fugate

Myung Sung Lee

Sang Ok Choi

Eun Seok Han

Joo Mun Lee

Oh Soo Kwon

Seung Hun Chae

Khee Park

Gi Y Jeon

A quadrifilar helical antenna comprising two pairs of filars having unequal lengths and phase quadrature signals propagating thereon. A conductive H-shaped impedance matching element matches a source impedance to an antenna impedance. The impedance matching element having a feed terminal at the center thereof from which current is supplied to the two filars of each filar pair disposed about an edge of the impedance matching element and symmetric with respect to a center of the impedance matching element. The impedance matching element further comprises a reactive element for matching the antenna and source impedances.

Quadrifilar helical antenna

A semiconductor contact bump structure is disclosed in which at least one contact bump is formed on an electrode pad of a semiconductor substrate through a contact window formed in a passivation layer on the semiconductor substrate. The contact bump has different lengths along respective perpendicular directions. In a first direction, the bump covers first edges of the passivation layer which define the contact window, while in a second direction, the contact bump is formed to be fully between second edges of the passivation layer defining the contact window. Such a construction results in a chip bump having an upper surface which is concavely curved along the first direction. By attaching leads to the bump along the second direction, junction resistance is advantageously lowered and noise generation is controlled to improve reliability of a semiconductor package. Also, shorting of the lead is prevented owing to the strong bonding force to improve yield of the semiconductor package.

Semiconductor chip contact bump structure

A chip-lifetime testing instrument for semiconductor devices which can detect defective chips by testing the performance and electrical lifetime of the chips in manufacturing process of the semiconductor devices, so that the manufacturing cost can be reduced and unnecessary processes for packaging of defective chips can be avoided, thereby reducing the necessary space for the set-up of the testing instrument.

Chip-lifetime testing instrument for semiconductor devices

A semi-conductor package having an insulator formed by a supporting portion, a mounting portion and connecting members, and a layer of electrically conductive material on the insulator in a pattern forming a pad and inner leads connected to the pad by supporting bars. A chip is attached on the pad, and the inner leads are wire-connected to the chip. The pad is vertically offset from the inner leads and the chip is supported in recessed fashion on the pad which shortens the length of the connecting wires whereby the wire-connecting efficiency and the structural stability are improved.

Semiconductor package

Growing community of inventors

Seoul, South Korea

Jin Hee Yoon