Industrial Technology Research Institute

Jin-Han Hsiao

Wei-Kuo Chia

Bao-Tyan Wang

An improved computer graphics memory architecture has a frame buffer and a Z buffer, each having a forward and reverse part, each of which is wide enough to handle two pixels of data. A data path is connected to the buffers so that in a 3-D application, a full pixel of both color and Z-value data is transported along the data path in a single I/O transaction. In a 2-D application, two pixels of data are transported along the data path in a single I/O transaction. In a preferred embodiment, both the frame and Z buffers are divided into two parts each wide enough to handle one pixel of data part. In 3-D applications, a data path is selectively connected to the buffers in a manner so that one pixel of color data and one pixel of Z-value data are simultaneously transported to the drawing processor during each I/O transaction. In this preferred embodiment, a first reversing switch such as a multiplexer circuit, is provided to reverse data that arrives from the buffer in reverse order. A second reversing switch, such as a multiplexer circuit, is provided to return the data to the proper buffer after processing. In a preferred embodiment for 2-D applications, two pixels of data are transported to the drawing processor each I/O transaction. In this preferred embodiment, a third reversing switch is provided to reverse data that arrives from the buffer in reverse order. A fourth reversing switch is provided to return the data to the proper buffer after processing.

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Chupei, Taiwan

Jin-Han Hsiao