Skhynix Inc.

S Hynix Inc.

Jin Ha Hwang

Yo Han Jeong

Soon Sung An

Keun Seon Ahn

Kwan Su Shon

Eun Ji Choi

Jaehyeong Hong

Junseo Jang

Jun Sun Hwang

Tai Sik Shin

Dong Shin Jo

Dong Hyun Kim

Dae Han Kwon

Kwang Soon Kim

Kyeong Min Chae

Dae Ho Yang

Dong Heon Lee

A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

Buffer circuit capable of reducing noise

An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.

Input/output circuit, operation method thereof and data processing system including the same

The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit

A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.

Data input buffer and semiconductor apparatus including the same

A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

Voltage generation circuit and input buffer including the voltage generation circuit

A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Signal receiving device, and a semiconductor apparatus and a semiconductor system including the signal receiving device

A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.

Dividing circuit system and semiconductor memory system including thereof

The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Data transmission circuit for preventing a node from floating and method of operating the same

An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

Buffer circuit and operating method thereof

An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

Memory device and operating method thereof

An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Impedance calibration circuit and semiconductor apparatus including the same

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

Growing community of inventors

Gyeonggi-do, South Korea

Jin Ha Hwang