Samsung Electro-Mechanics Co., Ltd.

Hynix Semiconductor Inc.

Skhynix Inc.

Samsung Electronics Co., Ltd.

Jin Gu Kim

Young Do Kweon

Seung Wook Park

Hyung Jin Jeon

Chang Bae Lee

Jong Yun Lee

Hee Kon Lee

Dong Hwan Lee

Young Ho Kim

Myung Sam Kang

Sang Kyu Lee

Mi Jin Park

Seon Hee Moon

Christian Romero

Ju Pyo Hong

Jin Su Kim

Young Seuck Yoo

Sung Woo Han

Ji Hyun Lee

Sung Yi

Yoon Su Kim

Yong Koon Lee

Sung Jae Chung

Joon Seok Kang

Jae Kul Lee

Myung Shik Lee

Seung Won Kim

Jung Woon Shim

Jong Hwan Baek

Jing Li Yuan

Su Min Yi

Yuan Jing Li

A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a heat sink structure comprising a lower heat sink pattern disposed on the first semiconductor chip, a metal film pattern disposed on the lower heat sink pattern, and an insulating film disposed on side walls of the lower heat sink pattern and side walls of the metal film pattern, an interposer disposed on the heat sink structure, and a solder ball which connects the heat sink structure and the interposer.

Semiconductor package

A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

Fan-out semiconductor package

A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.

Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via.

Printed circuit board and method of manufacturing the same

The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.

Via structure having open stub and printed circuit board having the same

Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a core layer having a first circuit wiring layer formed on one surface or both surfaces thereof; an insulating layer laminated, as at least one layer, on one surface or both surfaces of the core layer; and a second circuit wiring layer formed on one surface of the insulating layer, wherein a conductive core is included in upper and lower insulating layers contacting the second circuit wiring layer requiring an electromagnetic wave shielding, or the conductive core is included in the insulating layer or the core layer contacting the first circuit wiring layer requiring the electromagnetic wave shielding.

The present invention relates to a circuit board. A circuit board in accordance with an embodiment of the present invention includes a base substrate; an interlayer insulating layer covering the base substrate; a via structure passing through at least the interlayer insulating layer of the base substrate and the interlayer insulating layer in the vertical direction; and an etch stop pattern disposed on the interlayer insulating layer in the horizontal direction to surround the via structure and made of an insulating material.

Circuit board and method for manufacturing the same

Disclosed herein are a common mode filter and a method for manufacturing the same. The common mode filter includes a first insulator sheet; a first circuit layer having a first-layered first coil and a first-layered second coil alternately and separately arranged; a second insulator sheet laminated on the first circuit layer; and a second circuit layer having a second-layered first coil and a second-layered second coil alternately and separately arranged, the second-layered first coil being connected to the first-layered first coil and the second-layered second coil being connected to the first-layered second coil through the plurality of penetration holes.

Common mode filter and method for manufacturing the same

A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.

Flash memory device and method of programming the same

Disclosed herein is a circuit board including: a core layer including a via hole; a metal film covering an inner wall of the via hole; a circuit pattern connected to the metal film on the core layer; and a plug surrounded by the metal film in the via hole and having a thickness thinner than a thickness of the core layer.

Circuit board and method of manufacturing the same

Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.

Interposer-embedded printed circuit board

The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Stacked wafer level package and method of manufacturing the same

A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.

Method of forming metal line of semiconductor device

A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

Growing community of inventors

Gyeonggi-do, South Korea

Jin Gu Kim