Samsung Electronics Co., Ltd.

Jin-Goo Jung

Chun-Gi You

Kyung-Min Park

Jae-Byoung Chae

Tae-Ill Kim

Chul-Ho Kim

Il-Gon Kim

Hyun-Uk Oh

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent conductive layer on the first passivation layer; etching the transparent conductive layer using a photoresist as an etch mask to expose the portion of the first passivation layer and to form a pixel electrode connected the drain electrode; ashing the first passivation layer and the photoresist; and removing the photoresist.

Thin film transistor array panel and manufacturing method thereof

Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer.

Thin film transistor array panel including assistant lines

A thin film transistor array panel is provided, which includes: a semiconductor layer; a first insulating layer on the semiconductor layer; a gate line including a first amorphous silicon layer and a metal; a second insulating layer covering the gate line; and a data line formed on the second insulating layer. A variously tapered structure of the signal line may be formed by providing an amorphous silicon layer having good adhesion characteristics. The adhesion between the metal layer and the amorphous silicon layer may be improved by performing a thermal treatment process such that the contact resistance may be reduced therebetween. Accordingly, the characteristics and reliability of the TFT may be improved.

Multi-layered thin films, thin film transistor array panel including the same, and method of manufacturing the panel

A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A pixel electrode is formed. The first impurity is simultaneously implanted into partial portions of the pixel pattern part, the storage pattern part, and the driving pattern part.

Array substrate and method of manufacturing the same

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.

Thin film transistor array panel and method of manufacturing the same

In a display apparatus and a manufacturing method of the display apparatus, the display apparatus includes a display panel having signal lines and an insulating layer, and a signal generator electrically connected to the signal lines and adhering to the display panel. The signal lines include pads formed at ends thereof, respectively. The organic insulating layer is partially removed such that the via holes are formed between the pads of the signal lines to reduce a step-difference between an area in which the pads are formed and an area in which the pads are not formed. Thus, the display apparatus may enhance the coupling force between the signal generator and the display panel.

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Seoul, South Korea

Jin-Goo Jung