Samsung Electronics Co., Ltd.

Jin-gi Hong

Seong-deok Hwang

Gam-han Yong

Dong-hyuck Kam

Seung-Jae Lee

Sang-Hyun Lee

Sang-hyun Lee

Myoung-Bum Lee

Won-joo Kim

Ji-hyun Choi

Jong-Wan Choi

Jung-Chan Lee

Young-min Ko

Bo-young Lee

Woo-in Joung

Myeong-beom Lee

Chang-kyu Kim

Geung-won Kang

Young-jin Im

The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Light emitting device package

A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Non-volatile memory devices including low-K dielectric gaps in substrates

Methods of forming integrated circuit substrates include forming first and second trenches having unequal widths in a semiconductor substrate and then depositing a first oxide layer at a first temperature into the first and second trenches. The first oxide layer has a thickness sufficient to completely fill the first trench but only partially fill the second trench, which is wider than the first trench. A step is also performed to selectively remove a portion of the first oxide layer from a bottom of the second trench. A second oxide layer is then deposited at a second temperature onto the bottom of the second trench. The second temperature is greater than the first temperature. For example, the first temperature may be in a range from about 300&#xb0; C. to about 460&#xb0; C. and the second temperature may be in a range from about 500&#xb0; C. to about 600&#xb0; C.

Methods of forming oxide-filled trenches in substrates using multiple-temperature oxide deposition techniques

The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.

Method for manufacturing semiconductor device by forming insulator-layer

Growing community of inventors

Yongin-si, South Korea

Jin-gi Hong