Samsung Electronics Co., Ltd.

Jin-Gi Hong

Jung-Hun Seo

Young-Wook Park

Yun-Ho Choi

Hong-Gun Kim

Eun-Kee Hong

Ju-Seon Goo

Eun-Taeck Lee

Seung-Jae Lee

Jin-ho Kim

Hyeon-Deok Lee

Ji-soon Park

Jung-wook Kim

Won-Jin Kim

Eung-Joon Lee

Kyung-Bum Koo

Hyun Chul Kwun

Hyun-Chul Kwun

Disclosed are chamber inserts and apparatuses using the chamber inserts. A chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, a first protruding portion extending outwardly from a first portion of the cylindrical body portion, the first portion positioned circumferentially along the cylindrical body portion and a second protruding portion extending outwardly from a second portion of the cylindrical body portion, the second portion positioned circumferentially along less than all of the cylindrical body portion. In another example, the chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, the cylindrical body portion including a slit and at least one hole, the slit and the at least one hole positioned circumferentially along the cylindrical body portion and a first protruding portion extending outwardly from a first portion of the cylindrical body portion.

Chamber inserts and apparatuses for processing a substrate

In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

Method of forming a layer on a semiconductor substrate

In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.

Method of forming a layer and method of removing reaction by-products

In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjuted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.

Method for cleaning a processing chamber and method for manufacturing a semiconductor device

Disclosed are an electrode of a semiconductor device and a method of forming the same. A polysilicon layer is formed on a semiconductor substrate. An amorphous silicon capping layer is then formed on the polysilicon layer. A silicide layer is formed on the capping layer. The capping layer prevents chlorine ions from diffusing downward to the polysilicon layer. Accordingly, abnormal growth of the polysilicon layer can be prevented, thus improving the stability of the electrical characteristics of a semiconductor device electrode.

Gate electrode of a semiconductor device and method of forming the same

Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.

Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby

A method of forming a SOG insulation layer of a semiconductor device comprises forming the SOG insulation layer on a substrate having a stepped pattern by using a polysilazane in a solution state, performing a pre-bake process for removing solvent elements of the insulation layer at a temperature of 50 to 350&deg; C., performing a hard bake process for restraining particles from forming at a temperature of 350 to 500&deg; C., and annealing at a temperature of 600 to 1200&deg; C. The method of the invention further includes planarizing the insulation layer between the hard bake process and the annealing step. Also, the hard bake process can be omitted.

Method of forming a spin-on-glass insulation layer

A method of forming a SOG insulation layer of a semiconductor device comprises the steps of forming the SOG insulation layer on a substrate having a stepped pattern using a solution containing a polysilazane in an amount of less than 20% by weight in terms concentration of solid content, performing a pre-bake process for removing solvent ingredients in the insulation layer at a temperature of 50 to 350&deg; C., and annealing at a temperature of 600 to 1200&deg; C. The method of the invention further includes performing a hard bake process at a temperature of about 400&deg; C. between the pre-bake process and the annealing step. Also, the polysilazane is desirably contained in an amount of 10 to 15% by weight.

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Suwon-si, South Korea

Jin-Gi Hong