National Yunlin University of Science and Technology

Jin-Fa Lin

Ming-Hwa Sheu

Yin-Tsung Hwang

Cheng-Che Ho

Wei-Rong Ciou

Yu-Ru Cho

A low power pulse-triggered flip-flop comprises a latch containing a first conductive line and a first connection point and a pulse generator linking to the latch. The pulse generator includes a first N-transistor, a second N-transistor, a third N-transistor, a first inverter and a first P-transistor located on the first conductive line. The first N-transistor is connected to the first connection point and first conductive line. The second N-transistor and the third N-transistor are connected to the first conductive line, a second conductive line and a third conductive line. The first inverter is connected to the second conductive line. The present invention aims to reduce leakage power in a high level fabrication process, and can save power consumption and power-delay-product more than 17% over the conventional pulse triggered flip-flop, and also provides a smaller size of total transistors to lower average leakage current power consumption by 2.4 times.

Low power pulse-triggered flip-flop

A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate an adjustable pulse mode to solve the problem of threshold voltage loss.

Double-triggered logic circuit

In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.

Growing community of inventors

Chiayi County, Taiwan

Jin-Fa Lin