Korea Institute of Science and Technology

Jin-Dong Song

Joonyeon Chang

Won Jun Choi

Sanghyeon Kim

Hyunsu Ju

Hyun Woo Koo

Hyung-jun Kim

Suk Hee Han

Eunhye Lee

Il Ki Han

Subin Lee

Gyosub Lee

Sang Hoon Shin

Ju-Young Lim

Jae-Hoon Han

Jae Jin Yoon

Pavlo Bidenko

Jaehoon Han

Min Hwan Bae

Provided is a Group III-V compound semiconductor device. The device includes a substrate, a compound semiconductor layer provided on the substrate; and a buffer layer interposed between the compound semiconductor layer and the substrate. The compound semiconductor layer includes a first semiconductor area having a first conductivity type and a second semiconductor area having a second conductivity type. The buffer layer includes a high electron density area. In the buffer layer, an electron density of the high electron density area is higher than an electron density outside the high electron density area.

Group III-V compound semiconductor device

An optical phase shifter according to an embodiment for achieving the object of the present disclosure includes a first semiconductor layer formed on a substrate, a second semiconductor layer having opposite polarity to the first semiconductor layer, an insulating layer formed between the first semiconductor layer and the second semiconductor layer, and including ferroelectrics, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. According to an embodiment, the introduction of ferroelectric materials to a semiconductor-insulator-semiconductor (SIS) optical phase shifter brings about improvement in charge collection efficiency resulting from the negative capacitance effect, thereby achieving higher phase modulation efficiency and lower power consumption. Additionally, it is possible to realize a new structure of optical switch or modulator device through design changes of the type of ferroelectrics and the structural variables.

Optical phase shifter and optical switch device using ferroelectric material

A method for optical interconnection between semiconductor chips according to an embodiment include converting an electrical signal to an optical signal, transmitting the optical signal to a second substrate disposed above or below a first substrate using an optical transmitter provided on the first substrate, receiving the optical signal using an optical detector provided on the second substrate, and converting the received optical signal to an electrical signal. Accordingly, using a mid-infrared wavelength range of light that is transparent to semiconductor materials such as silicon and next-generation high-mobility materials, it is possible to enable interconnection between stacked semiconductor chips without using metal wiring. Using optical interconnection, it is possible to significantly reduce the bandwidth and power consumption, and overcome the limitations of TSV technology, and it is possible to extend the photonics technology and platform established in the existing Si Photonics, thereby reducing the cost required for design.

Method for optical interconnection between semiconductor chips using mid-infrared

In an aspect of the present disclosure, there is disclosed a manufacture method of an antireflection coating using a self-assembly nano structure, which includes forming a first metal droplet on a substrate by means of droplet epitaxy, depositing a first non-metal on the formed first metal droplet, and forming a first nano compound crystal by means of self-assembly of the deposited first non-metal and the first metal droplet.

Antireflection coating using self-assembly nano structure and manufacture method thereof

Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

P-type semiconductor device comprising type-2 quantum well and fabrication method thereof

Disclosed is a method of manufacturing a semiconductor device whereby InAsSbsemiconductor layer is formed on an easily available and economical semiconductor substrate such as a GaAs substrate or a Si substrate. According to the method, a quantum dot layer is formed between a semiconductor substrate and a semiconductor layer to reduce defects caused by lattice mismatch between the semiconductor layer and the semiconductor layer. The method may improve the growth speed of the semiconductor layer. In addition, because the InSb layer provided by the present invention has an electron mobility greater at room temperature, it may improve the quality and productivity of the semiconductor device.

Method of manufacturing In(As)Sb semiconductor on lattice-mismatched substrate and semiconductor device using the same

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Seoul, South Korea

Jin-Dong Song