Mediatek Corporation

Mediatek Incorporation

National Science Council

Jin-Bin Yang

Yu-Hsuan Lin

Hsi-Chia Chang

Rei-Fu Huang

Yi-Kwang Hu

Pi-Hai Liu

Chih-Ching Chen

Tzi-Dar Chiueh

Jia-Horng Shieh

Meng-Ta Yang

Ming-Yang Chao

Chao-Long Tsai

Gwo-Huei Wu

Jen-Shi Wu

Ching-Ning Chiu

Kuen-Suey Hou

An eFuse with at least one fuse unit is provided. The fuse unit includes a first common node providing a first reference voltage, a second common node providing a second reference voltage, at least one fuse coupled to the first common node, and a determining unit coupled between the fuse and the second common node, generating an output signal indicating whether the fuse is blown or not according to a first condition in a normal mode and a second condition in a test mode.

eFuse macro

An eFuse with at least one fuse unit is provided. The fuse unit includes a common node, a sensing unit with a first input terminal and a second input terminal, at least one fuse coupled between the common node and the first input terminal of the sensing unit with a resistance, and a switching unit coupled between the common node and the second input terminal of the sensing unit. A resistance of the switching unit is equivalent to a first resistance in a normal mode and equivalent to a second resistance in a test mode, and the second resistance is higher than the first resistance. The sensing unit generates an output signal indicating whether the fuse is blown or not according to the resistances of the fuse and the switching unit.

The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M(x)), a second polynomial (M(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G(x)); next, dividing M(x)xby G(x) to obtain a first remainder polynomial (R(x)); next, generating a second code generator polynomial (G(x)) from G(x); next, generating a third polynomial (M(x)); next, dividing M(x)xby G(x) to obtain a second remainder polynomial (R(x)); next, performing an adding procedure to R(x) and R(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).

Encoding method and apparatus for cross interleaved cyclic codes

An apparatus for controlling discrete data in a disk overwrite area or a power calibration area comprises a signal-processing unit, an address-processing unit, a control signal-processing unit, a clock recovery circuit, a signal-processing unit parameter control unit, and a clock recovery circuit parameter control unit, wherein the control signal-processing unit uses a message produced by a data on the disc to determine the control signals such as hold, load, or increasing bandwidth for holding, loading, and increasing the bandwidth of the parameters for processing the related circuits (such as the circuit of the signal-processing unit or the clock recovery circuit) of the discrete data produced between the two data clusters, so as to increase the convergent speed of the circuits for assuring the accuracy of reading data.

Apparatus for controlling discrete data in disk overwrite area or power calibration area

A data buffering method used when performing a read operation on an optical storage medium is disclosed. After a first data unit having an unidentifiable and temporarily undeducible ID address is reproduced through the read operation, the method starts storing the first data unit and subsequently reproduced data units into a buffer memory in turn. After a second ID address of a second data unit of the subsequently reproduced data units is identified, the method deduces a target memory address of the buffer memory according to the second ID address and a target ID address. A buffer start pointer is then set according to the deduced target memory address.

Data buffering method used when performing read operation on optical storage medium

Disclosed is a data search system for searching the data sync pattern by using a physical address or by detecting the falling edge of the blank area end. The data search system comprises a first data start indicator, a second data start indicator, a decision circuit, a window generator and a data sync pattern search circuit. The first data start indicator generates a first start search signal indicating a first start position. The second data start indicator generates a second start search signal indicating a second start position. The decision circuit selects to output one of the start search signals. The window generator generates a window interval starting from the start position. The data sync pattern search circuit searches a data sync pattern of the data in the window interval to determine the data following the data sync pattern.

Data search system for searching a data sync pattern in optical disc and method thereof

A control circuit and a control method of controlling a rotation frequency of a spindle in an optical disc drive, the control circuit comprising: a spindle controller, electrically coupled to the spindle, for driving the spindle to rotate an optical disc according to a rotation control signal; a detector, electrically coupled to the spindle controller, for detecting the rotation frequency and for generating detecting signals; a frequency-adjusting module, electrically coupled to the detector, for adjusting at least one of the detecting signals to reduce a rotation frequency difference between detecting signals; a signal selector, electrically coupled to the frequency-adjusting module, for receiving output signals generated from the frequency-adjusting module and then outputting the rotation control signal.

Control circuit and method of controlling rotation frequency of spindle in optical disc drive for reducing frequency difference of output signals respectively corresponding to different disc rotation modes

The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M(x)), a second polynomial (M(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G(x)); next, multiplying M(x) by xand dividing the product of M(x)xby G(x) to obtain a first remainder polynomial (R(x)); next, generating a second code generator polynomial (G(x)) from G(x); next, generating a third polynomial (M(x)); next, multiplying M(x) by xand dividing the product of M(x)xby G(x) to obtain a second remainder polynomial (R(x)); next, performing an adding procedure to R(x) and R(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).

A modulation method for a first data string having a plurality of symbols is disclosed. The method includes: appending a data string to the first data string to form a second data string; and converting the second data string to a code word sequence by converting each of the symbols in the first data string to a code word according to predetermined modulation rules and a symbol set selected from the second data string. Each code word has a first fixed number of bits, each symbol has a second fixed number of bits, and each symbol set has a fixed number of symbols.

Method and apparatus for encoding/decoding in fixed length

A phase locked loop (PLL) generates a phase locked signal and adjusts a frequency of the phase locked signal according to an incoming signal. The PLL includes an oscillator for generating the phased locked signal and a frequency detection module electrically coupled to the oscillator. The frequency detection module includes a pattern detector for detecting the two regular patterns in the incoming signal, a counter electrically coupled to the pattern detector for calculating the number of periods of the phase locked signal corresponding to the distance between the two regular patterns, and a comparator electrically coupled to the counter for comparing the number of periods with a predetermined value to generate a control signal, and using the control signal to control the oscillator to adjust the frequency of the phase locked loop signal.

High resolution phase locked loop

The invention advantageously provides an apparatus and method for recovering clock signals extracted from prerecorded wobbled grooves formed in an optical storage medium such as a compact disk (CD), mini disk (MD) or digital video disk (DVD). A preferred embodiment of the method according to the invention primarily comprises the steps of extracting a series of wobble signals from the prerecorded information, demodulating the wobble signals for generating a series of demodulated clock signals, detecting a period for the clock signals, dividing each of the clock signals for acquiring a series of synchronization frames, generating compensating phases, and respectively adjusting the synchronization frames with the compensating phases for generating a series of phase compensated frames.

Apparatus and method for recovering clock signal extracted from prerecorded information in optical storage devices

The present invention provides a control loop bandwidth adjusting system for adjusting a control loop bandwidth of an optical reproducing device. The optical reproducing device comprises a data signal processing circuit, which uses the control loop bandwidth to process the data signal. The control loop bandwidth adjusting system comprises a control loop bandwidth generator for generating the control loop bandwidth and a control loop bandwidth according to whether a defect signal corresponding to the defect data is received or not. If the control loop bandwidth adjusting module receives the defect data entry signal, the defect data duration signal, and the defect data exit signal, the control loope bandwidth is adjusted to a first bandwidth value, a second bandwidth value, and a third bandwidth value respectively.

System and method for adjusting a control loop bandwidth

A mixed-signal-controlled phase-locked loop is provided. This loop includes a mixed-signal-controlled oscillator circuit for generating an oscillating signal having an oscillating frequency and a phase in response to a digital control signal and an analog control signal, a phase-frequency detector circuit electrically connected to the mixed-signal-controlled oscillator circuit, detecting the phase and the oscillating frequency of the oscillating signal and comparing the phase and the oscillating frequency with those of a reference signal to generate an error signal after the phase and oscillating frequency are detected, and a mixed-control-signal-producing circuit electrically connected to the mixed-signal-controlled oscillator circuit and the phase-frequency detector circuit for receiving the error signal to output the analog control signal and the digital control signal to the mixed-signal-controlled oscillator circuit.

Growing community of inventors

Changhua County, Taiwan

Jin-Bin Yang