Intel Corporation

Jimmy W Wong

Sunil R Shenoy

Jay S Heeb

Badarinath N Kommandur

An instruction translation look-aside buffer (iTLB) for attaining very high data processing throughput comprises a 2.sup.n -way set associative data array having m sets, where m and n are both integers greater than or equal to one, with associated data and tag arrays. A set address selects one of the m sets for reading, resulting in a readout of all 2.sup.n ways of the tag, valid and data arrays. Comparison logic determines if a match exists between the 2.sup.n tags read out from the tag array with a portion of the linear address. A 'hit' to a certain way causes a hit line signal to select data for the corresponding way, which is output from a 2.sup.n :1 static multiplexer and contains the physical address translation. Each of the hit lines are precharged during a first phase of a clock cycle. The comparison logic operating during a second phase of a clock cycle. Thus, the matching is accomplished in a single clock cycle.

Single phase pseudo-static instruction translation look-aside buffer

A microprocessor and method which allows data consistency to be maintained between a memory which is external to the microprocessor and a data cache unit. The microprocessor has a central processing unit coupled to a local bus. A direct memory access unit coupled to the central processing unit for loading data from and storing data to the direct access memory unit. The local bus is coupled to a system bus and has a bus control unit controlling the loading and storing of data on the system bus. The system bus transfers data external to the microprocessor using the bus control unit upon instructions from the central processing unit. A data cache unit is coupled to the local bus and selectively stores a copy of data loaded by the bus control unit and receives a memory address from the local bus during a memory access by either the central processing unit or the direct memory access unit. The microprocessor employs a mechanism that invalidates copy data when the memory access is a store by the direct memory access unit when a cache hit is detected. Further, the microprocessor employs a mechanism that designates as non-cacheable the loading of data by the direct access memory unit, even though the data was previously designated as cachable, preventing the data cache unit from performing any action, namely the overwriting of more critical data within the data cache unit.

Method and apparatus for using a direct memory access unit and a data

A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to allow sufficient time for 'hit or miss' detection by a data cache unit. The present invention dynamically expands the instruction pipeline for cacheable LOAD instructions that 'miss' an on-chip data cache when the LOAD is followed by another instruction that uses the bus controller. The dynamic pipeline allows time for the 'hit or miss' detection by the data cache unit without unnecessarily degrading pipeline performance. The present invention offers increased overall microprocessor and computer system performance by allowing efficient implementation of an on-chip data cache. The present invention provides increased performance without undue or overly complex modifications to existing pipeline or data cache circuits.

Method and apparatus for dynamically expanding the pipeline of a

A memory coprocessor architecture and memory arbitration scheme. The coprocessor architecture includes an address generation unit (AGU), a bus control logic unit (BCL) and a combined data cache unit/stack RAM (DCUSR) unit. Each are connected through a memory arbitration unit to a data bus. The memory arbitration unit arbitrates access to the bus by assigning priorities to the coprocessor units. The AGU and the combined DCUSR are mutually exclusive coprocessors which cannot request bus access simultaneously. Hence, the AGU and the combined DCUSR are assigned equal priorities. The BCL is assigned a lower priority and must defer bus access if the AGU or the DCUSR require immediate access. The BCL is provided with a multiple entry queue for storing data temporarily pending access to the queue. A memory scoreboard mechanism is provided such that, if the queue of the BCL becomes full, the BCL can gain immediate access to the bus to allow emptying at least one entry of the queue. The combined DCU and SR share common decoders, sense amps and data paths.

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Portland, OR, United States of America

Jimmy W Wong