Lsi Logic Corporation

Broadcom Corporation

Jimmy S Wong

Daniel R Watkins

Yen C Chang

Jeffrey A Werner

Pavlina Ennghillis

Various example embodiments are disclosed. According to an example embodiment, a network device may include a memory management unit. The memory management unit may be configured to populate a count field based on a number of equal cost paths for each Internet Protocol (IP) route for a packet, randomly choose one of the equal cost paths for the packet, and send the packet out of the network device, the packet including route information for the chosen equal cost path.

Selecting a path for a packet

A method of replicating multicast datagrams in a network device is disclosed. The method includes the steps of determining by a memory management unit whether a scheduled outgoing datagram stored in a main memory is a multicast (MC) packet. When the scheduled outgoing datagram type is the MC datagram, the method also includes performing a lookup of a replicate count table to determine a copy count value and writing the copy count value to a copy count register, awaiting a ready signal from an egress port of the network switch and sending the outgoing datagram to the egress port from the main memory along with the copy count value. The method also includes changing the copy count value in the copy count register, modifying a VLAN identifier of the outgoing datagram if necessary based on the copy count value and forwarding the outgoing datagram from the egress port.

Datagram replication in internet protocol multicast switching in a network device

A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.

Logic compiler for design of circuit models

A periodic sequence of signals is intiated and provided to a counter. During this time, a pulse (PULSE) is generated. Upon reaching a terminal count the pulse is terminated. The pulse is provided to a delay element which receives at its input a signal (s) entering, processed within or exiting a semiconductor device. The pulse and periodic sequence of signals are initiated by an edge detector detecting a trigger signal (TRIGGER), which may be the signal (s) being delayed. The sequence of signals is generated by a circuit element, such as a ring oscillator, and the periodicity of the sequence of signals is related to the inherent switching speed of the semiconductor device technology. A plurality of delay circuits are provided in a semiconductor device for individually delaying a plurality of signals entering, processed within and exiting the device. A library of delay circuits may pre-designed, and stored for implementation, as needed, in semiconductor devices. The delay imposed on signals entering, processed within and exiting the device is readily modified by modifying the periodicity of the sequence of signals and/or modifying the terminal count. Method and apparatus are disclosed.

Configurable pulse generator, especially for implementing signal delays

A general purposes architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optional ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and macroinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

Flexible ASIC microcomputer permitting the modular modification of

A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.

Growing community of inventors

Cupertino, CA, United States of America

Jimmy S Wong