Mips Technologies, Inc.

International Business Machines Corporation

Advanced Micro Devices Corporation

Altera Corporation

Kilopass Technology, Inc.

Jimmy Lee Reaves

Charles Edwin Cox

David Hugh McIntyre

Marc A Miller

For a block of memory cells interconnected by single-ended bit lines, a sense amplifier receives the input from a single-ended bit line to determine the logic state of a selected memory cell connected to the single-ended bit line. The sense amplifier also receives a reference voltage generated from a base-emitter voltage of a emitter follower bipolar transistor. The base-emitter voltage is controllably divided by a voltage divider network with selectable resistive elements to tune the reference voltage.

Tunable sense amplifier reference for single-ended bit lines

An integrated circuit (IC) that includes content addressable memories (CAM) is described. A CAM receives a key and searches through entries stored in the CAM for one or more entries that match the key. If a matching entry is found, the IC returns a storage address indicating a memory location at which the matching was found.

Content addressable memory in integrated circuit

A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.

Multi-port memory array

A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record.

Method and system for emulating content-addressable memory primitives

An apparatus for generating multi-phase signals includes a delay chain to produce multi-phase signals, a slow boundary signal, and a fast boundary signal. An array of trim capacitors is connected to the delay chain. A timing control window circuit produces a control signal when a reference signal is outside a timing control window defined by the slow boundary signal and the fast boundary signal. A digital circuit produces a digital capacitive trim signal for application to the array of trim capacitors in response to the control signal. The digital capacitive trim signal alters the capacitive loading of the delay chain.

Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors

An article of manufacture describes and simulates a logic device that detects the all-zero scenario for an n-bit word. The n-bit word has a selected bit that is defined using a high-inactive convention, and (n&minus;1) non-selected bits that are defined using a high-active convention. The article of manufacture is embodied as a computer useable medium configured to store computer program codes that describe and simulate the logic device. The logic device described by the computer program codes includes an output FET, a pre-charging circuit, a first evaluation circuit, and (n&minus;1) second evaluation circuits. The pre-charging circuit charges the output FET gate, drain, and source to a pre-charge voltage during a low clock cycle. During a high clock cycle, the first evaluation circuit evaluates the selected bit and discharges the pre-charge voltage on the output FET source if the selected bit is a voltage high. The (n&minus;1) second evaluation circuits evaluate the non-selected bits and maintain the pre-charge voltage on the output FET gate if each of the non-selected bits is a voltage low. The output FET conducts if the pre-charge voltage is maintained on the output FET gate and if the output FET source is discharged to ground. The drain of the output FET discharges to a low voltage if the output FET conducts, which indicates the all-zero scenario for the n-bit word.

Output synchronization-free, high-fanin dynamic NOR gate

An output synchronization-free NOR gate detects the all-zero scenario for an n-bit word. The n-bit word having a selected bit that is defined using a high-inactive convention, and (n&minus;1) non-selected bits that are defined using a high-active convention. The NOR gate includes an output FET, a pre-charging circuit, a first evaluation circuit, and (n&minus;1) second evaluation circuits. The pre-charging circuit charges the output FET gate, drain, and source to a pre-charge voltage during a low clock cycle. During a clock high cycle, the first evaluation circuit evaluates the selected bit and discharges the pre-charge voltage on the output FET source if the selected bit is a voltage high. The (n&minus;1) second evaluation circuits evaluate the non-selected bits and maintain the pre-charge voltage on the output FET gate if each of the non-selected bits is a voltage low. The output FET conducts if the pre-charge voltage is maintained on the output FET gate and if the output FET source is discharged to ground. The drain of the output FET discharges to a low voltage if the output FET conducts, which indicates the all-zero scenario for the n-bit word.

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San Jose, CA, United States of America

Jimmy Lee Reaves