Cadence Design Systems, Inc.

Other

Jimmy Kwok-Ching Lam

Limin He

Mark Steven Hahn

Jianmin Li

Stefanus Mantik

Soohong A Kim

Chris Morrison

Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.

Computationally efficient design rule checking for circuit interconnect routing design

An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all targets of each partition are triggered by a common clock edge. Specifying timing constraints in partitions can provide an efficient method of determining how much slack, if any, is present in the timing of a design.

System and method for generating and using stage-based constraints for timing-driven design

A method for determining the location of electric leaf cell circuits within the architecture of a semiconductor chip includes determination of the longest signal delays through an electric leaf cell circuit by evaluating independent channel connected components, reorganizing the circuit elements of each channel under evaluation into acyclic form, restructuring the acyclic form of channel connected components within the electric leaf cell circuits being structurally positioned in the chip architecture by selected reduction processes, determining input state vectors for each input and output pin connection pair of the electric leaf cell circuit in which an input pin connection state change is reflected in an output connection pin state change, and determining placement of the leaf cell within a semiconductor circuit module with reference to the greatest delay within each leaf cell.

Method for electric leaf cell circuit placement and timing determination

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Cupertino, CA, United States of America

Jimmy Kwok-Ching Lam