Integrated Device Technology, Inc.

Synaptics Corporation

Jimmy J Lee

Chuen-Der Lien

Howard Chonghe Yang

Frank Hwang

Henry Zeng

Daniel J Liao

Joe F Santandrea

A multi-monitor display is disclosed. A multi-monitor display receives video data configured for a single N&#xd7;M video display; splits the video data into a plurality of portions spanning the N&#xd7;M display; and transmits the plurality of portions to a corresponding plurality of displays. The multi-monitor display system can be any system, for example a display-port system or an ePaper system.

Multi-monitor display system

A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.

Clock generator and method for providing reliable clock signal using array of MEMS resonators

A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such.

Method and apparatus for clock generation

A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset values(s), and combinations of such.

A passive semiconductor structure for reduction of the mutual capacitance between parallel conductors, with two parallel conductors separated from a substrate by a first dielectric layer and covered by a second dielectric layer. The second dielectric layer having a cavity formed between these conductors, whereby the effective relative dielectric constant of the medium between these conductors is reduced.

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Palo Alto, CA, United States of America

Jimmy J Lee