Via Technologies, Inc.

Chunghwa Picture Tubes, Ltd.

Jimmy Hsu

Chi-Hsing Hsu

Moriss Kung

Kwun-Yao Ho

Jay Yu

Nicole Li

Randy Hsiao

Teddy Chou

Min-Sheng Lin

Ted Hsu

A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

Testing circuit and related method of injecting a time jitter

A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole and extended through the through hole. The reference line is disposed on a portion of the inner surface of the through hole and extended through the through hole, wherein the reference line is disposed between the lines for signal. Because the signal lines are separated by the reference line, the electromagnetic coupling generated by signals can be reduced to lower the cross-talk interference between signals passing through the through hole, so as to promote the signal-transmission quality.

Multi-conducting through hole structure

A signal transmission structure is provided. The structure mainly comprises at least a conductive via, at least a via land and a conductive wall. One end of the conductive via is connected to the via land. The conductive wall covers only a portion of the inner wall of a through hole in the core layer of a circuit substrate. The conductive wall has a semi-circular or a C-shaped structure. Therefore, when a signal passes the conductive via and the via land of the circuit substrate through the conductive wall in the interior of the via, because of a more continuous impedance between the via land and the conductive wall, signal reflection due to impedance mismatch along the signal transmission pathway can be reduced to enhance signal transmission quality.

Signal transmission structure and circuit substrate thereof

A multi-layered substrate has a voltage reference signal circuit layout therein. A major change in the design of the multi-layered substrate is the moving of a reference signal trace from a signal layer to a non-signaling layer. Once the reference signal trace is moved, the signal traces within the signal layer can have a larger layout area. Similarly, the reference signal trace within the non-signaling layer can have greater layout flexibility in addition to electromagnetic shielding from other signal traces. Moreover, the reference signal trace having a greater width may be used to reduce parasitic resistance within the reference signal circuit.

Voltage reference signal circuit layout inside multi-layered substrate

The methodology includes a single excitation analysis, a multi-excitation analysis, and a simultaneous switch noise, SSN, analysis. A chip connects to the PDS at a plurality of power ports formed by pads for obtaining biasing voltage and current from those power ports. The single excitation analysis includes respectively making each of power ports start conducting current, and measuring a voltage provided by the power port. An equivalent impedance of each power port is obtained. The multi-excitation analysis includes making a given power port conduct a given current, and measuring voltages at other power ports for evaluating mutual couplings across different power ports. The SSN analysis includes respectively making different numbers of power ports conduct currents and accordingly evaluating different equivalent impedances corresponding to different SSN situations.

Method for analyzing power distribution system and related techniques

A signal transmission structure including a signal line, a first reference plane with a first opening, and a second reference plane with a second opening is provided. The first reference plane is disposed beside the signal line, and a portion of the signal line passes through a position of the first opening. In addition, the second reference plane is disposed beside the first reference plane, and the second opening is in a position corresponding to the position of the first opening, while the outline of the second opening projected onto the first reference plane does not overlap with the position of the first opening. Therefore, at high frequency-transmission, the above structure can reduce the insertion loss resulted from impedance mismatch as the signal passes through the opening, and reduce the resonance induced by the coupling between two reference planes to enhance the quality of signal transmission.

Signal transmission structure having plural reference planes with non-overlapping openings

A signal transmission structure is provided. The signal transmission structure has salients. The salients are corresponding to the position of the non-reference region and protrude from a lateral side of the signal traces. When the signals are transmitted on the signal traces, the parasitic capacitance between the salients and the reference plane can improve the characteristic impedance mismatch. Hence, when the signals are transmitted in a high frequency/high speed environment, the salients of the signal transmission structure reduce the effect of the near-end and far-end crosstalk generated by the other signal trace when a signal trace passes through a non-reference region, in order to keep the good quality of the signals.

Signal transmission structure having salients aligned with non-reference regions

The chip package comprising a package substrate, a circuit layer, a chip and at least one conductive wire is provided. The circuit layer is disposed on a first surface of the substrate, and extends from the first surface to a second surface of the substrate via the inner surface of a slot of the substrate. The chip is disposed on the second surface of the substrate to cover the slot and a portion of the circuit layer. The chip has at least one signal pad and at least one non-signal pad. The non-signal pad is electrically connected to the circuit layer on the second surface. The slot in the substrate exposes the signal pad. One end of the conductive wire passing through the slot is connected to the signal pad while the other end thereof is connected to the circuit layer on the first surface of the substrate.

Chip package

A signal transmission structure is provided. The structure comprises a reference plane, a bonding pad, a conductive trace and a conductive ball. By changing the shapes of the reference plane and the conductive trace, the equivalent capacitance at the conductive ball and the signal route near the conductive ball is reduced, or the equivalent inductance at the conductive ball and the signal route near the conductive ball is increased to compensate the high equivalent capacitance between the conductive ball and the reference plane. Therefore, the impedance of the conductive ball and the signal route near the conductive ball are matched to increase the integrity of the signals after these signals pass through the conductive ball and the signal neighbor route near the conductive ball.

Signal transmission structure having a non-reference region for matching to a conductive ball attached to the signal transmission structure

A surrounding structure of a probe card is described, and particularly an isolator unit, which is formed by filling in a wire leading region with epoxy material to substitute for an originally clear portion, so as to improve high impedance characteristics of the cross-over portion by using the resultant parasitic capacitance effect, and improve the compensation for the purpose of impedance matching. Additionally, the energy loss is reduced and the application frequency range is widened.

Surrounding structure for a probe card

A signal transmission structure includes at least one reference plane with a non-reference area, and a signal line with a salient protruding over the edge of the signal line and the salient is corresponding to the position of the non-reference area. When a signal passes through the signal line, the effect of the parasitic capacitance between the salient and the reference plane can improve the characteristic impedance mismatch. Therefore, the signal transmission structure can reduce the insertion loss and increase the reduction of the return loss in order to locally compensate the impedance mismatch.

Signal transmission structure

The present invention is a bonding pad structure for improving impedance matching that can optimize the impedance matching of the loop between the chip and the substrate inside the package so as to improve the electrical characteristics of the package structure by increasing the capacitance of the loop through a simple structural refinement of the bonding pad structure. The aforesaid bonding pad structure has function of signal transmission and grounding for electronic components having multiple electrical-connected layers, furthermore, the feature of the foregoing structure is as following: the space between two bonding pads exists a metal structure constructed using a plurality of parallel-positioned metal layers which are overlapping and disconnected to one another.

Bonding pad design for impedance matching improvement

A printed circuit transformer includes a first wiring layer, a second wiring layer, a primary conductive coil including a first conductive trace, a second conductive trace, a third conductive trace, and a fourth conductive trace, which are on the first wiring layer or the second wiring layer, a first via plug, a second via plug, and a third via plug for connecting the ends of the conductive traces in the primary conductive coil, and a secondary conductive coil including a fifth conductive trace, a sixth conductive trace, a seventh conductive trace, and a eighth conductive trace, which are on the first wiring layer or the second wiring layer, a fourth via plug, a fifth via plug, and a sixth via plug for connecting the ends of the conductive traces in the secondary conductive coil.

Transformer former between two layout layers

A chip package structure with a guard circuit design. The individual wires of two pairs of ground wires are positioned on each side of a high frequency signal wire so that external interference is minimized during transmission, multiple ground contacts are provided and current routes are shortened. In the meantime, strength of the electromagnetic field produced by the high frequency signal wire during transmission is limited within the pairs of ground wires. Ultimately, the range of interference by the electromagnetic field, the insertion loss and the return loss are all reduced resulting in improved performance of the chip package.

Chip package structure

A flip-chip package substrate layout for reducing plan inductance. The flip-chip package substrate includes a plurality of sequentially stacked wiring layers, at least one insulation layer between two neighboring wiring layers so that the insulation layer and the wiring layers are alternately stacked on top of each other, and a plurality of conductive plugs individually penetrating the insulation layer for electrically connecting the wiring layers. The uppermost wiring layer has at least one power pad region, which has a plurality of power bump pads, while the bottommost wiring layer has a plurality of bonding pads. The position of the power pad region maybe interchanged with the neighboring ground pad region. In addition, two ends of the power pad region may also be extended toward the ground pad region. Hence, the power bump pads located at the two ends of the power pad region are respectively electrically connected to one of the bonding pads through the wiring layers and the conductive plugs.

Growing community of inventors

Taipei Hsien, Taiwan

Jimmy Hsu