International Business Machines Corporation

Jimmy G Foster

Timothy Jay Dell

Gregory David Sellman

Louis Bennie Capps, Jr

Warren D Bailey

Sumanta Kumar Bahali

Warren E Price

Kenneth Allen Uplinger

Robert W Rupe

A power management server and method for managing power consumption is disclosed. According to one embodiment, a power management server data processing system is provided, where the power management server data processing system comprises a power management communication port to communicatively couple the power management server data processing system to a power-managed server data processing system and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises power management logic configured to receive power management data from the power-managed server data processing system, to generate a power management command utilizing the power management data, and to transmit the power management command to the power-managed server data processing system utilizing the power management communication port. Moreover, the power management data of the described embodiment comprises power management capability data.

Power management server for managing power consumption

A SIMM is provided which adds ECC onto a computer system, which system does not have ECC capabilities. The SIMM has ECC on board. The SIMM also has logic to sense whether the system is an 'even' parity or 'odd' parity system. Parity of the written data bytes is checked, and check bits used for the ECC are manipulated to check parity on the read cycle responsive to the sensed parity of the system. During the read cycle, parity is generated by the logic corresponding to the sensed system parity, and ECC is performed.

Method and structure for providing automatic parity sensing

Method and structure for providing error correction code and automatic

A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

Personal computer memory bank parity error indicator

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Boca Raton, FL, United States of America

Jimmy G Foster