Ncr Corporation

Jimmy D Pike

Gene F Young

Arthur F Cochcroft, Jr

Craig A Walrath

Jeffrey Forest McElroy

Edward A McDonald

Thomas F Heil

Robert Samuel Cooper

James L Browning

Daniel C Robbins

P Chris Raeuber

A reporting system for a computer network. A server in the computer network monitors error status of various components within the network. When the error status indicates that human intervention is required, the server contacts a system manager, through a cellular telephone network. The server delivers a message indicating the error status to the manager, as by a synthesized speech message which describes the status.

Computer system management using dedicated cellular appliance

A digital processing system including a central processing unit (CPU) and a digital signal processor (DSP) is optimized for digital signal processing applications, providing the central processing unit and digital signal processor with equal access to system resources such as system memory and connected I/O devices. The digital processing system includes two high-performance processor busses: one processor bus providing connection for one to four CPUs; the other processor bus providing connection for up to four DSPs. An advanced multi-ported memory controller interconnects the two processor busses with system memory and a system I/O bus, providing the CPUs and DSPs with equal and uniform access to all system memory and I/O resources.

Computer system including a digital signal processor and conventional

A communications-oriented computer system backplane including an input/output bus for transmission of address, data, and control information, the input/output bus including a plurality of expansion slot module connected to the input/output bus for the connection of I/O logic cards; and a time-domain multiplexed signal bus (TDMSB) for transmission of high-speed digitized signal information, the time-domain multiplexed signal bus including a plurality of expansion slot modules connected to the time-domain multiplexed signal bus for the connection of high-speed digitized signal logic cards. The expansion modules associated with the two busses are aligned to facilitate interconnecting the input/output bus with the time-domain multiplexed signal bus for transmitting data therebetween.

Communications-oriented computer system backplane including a PCI

A multischeme memory management system for large memory computer systems which combines traditional hardware based memory management with a versatile software based memory management scheme. The memory management system includes a conventional memory handler implemented in hardware for managing memory addresses below a fixed limit, for example four gigabytes; and a plurality of memory handlers implemented in software for managing memory addresses greater than four gigabytes. A programmable memory range detectors is associated with each software implemented memory handler. Memory handlers are selected by addressing the different memory address ranges programmed into the memory range detectors. The memory range detectors associated with the software implemented memory handlers are also prioritized so that lower priority memory range detectors are disabled when a higher priority memory range detector receives an address included within its memory range, thereby resolving conflicts which may otherwise occur when address ranges overlap. The range of addresses associated with the lowest priority memory range detector may be defined to include all memory addresses, thereby establishing the lowest priority memory range detector and its associated software implemented memory handler as defaults for memory addresses greater than four gigabytes.

Multischeme memory management system for computer

An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.

System for preventing an unselected controller from transferring data

Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Architectures for computer systems having multiple processors, multiple

Process migration is controlled in multiple processor system by a circuit providing a rapid lookup to see if an available process has any affinity for the top N entries on the system run queue. If the currently available processor has an affinity for, i.e. has one or more lines of operands and/or instructions stored in its local cache related to the process, then the processor selects the process it has affinity for from the top N processes on the run queue. In this manner, unnecessary replacements of cache lines with data from main memory is reduced.

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Lexington, SC, United States of America

Jimmy D Pike