Harris Corporation

Jimmy C Black

Bruce E Roberts

Dyer A Matlock

George E Mraz

Charles M Dalton

The conducting layer, such as polysilicon, which electrically connects spaced apart semiconductor islands of a semiconductor-on-insulator, such as sapphire, integrated circuit device is further spaced from the base, sides and upper edges of the islands (identified as sites for origination of undesirable leakage currents during operation) by an underlying insulating layer which may include silicon oxide with a dopant such as phosphorus or boron. During processing, the islands provide a self-masking effect when illumination is first passed through the sapphire substrate to expose photoresist. Refraction of the illumination around the upper edges of the islands provides a convenient way to form the insulating layer so that it lips over the edges and slightly onto the top of the islands.

Fabricating dielectric isolation of SOI island side wall for reducing

Dielectric isolation for SOI island side wall for reducing leakage

Formation of an interconnect structure having a self-planarized dielectric layer between successive layers of metallization is accomplished by conformally depositing a dielectric layer over the entire structure (including underlying regions and contact base metallization) to which the interconnect pattern is to be plated. Atop the dielectric layer a sacrificial layer is conformally deposited. Thereafter apertures are etched through both the sacrificial and dielectric layers in accordance with a prescribed interconnect plating pattern that has been photolithographically mapped onto the laminate structure. The aspect ratios of the apertures through the laminate are such that metal to be subsequently deposited therethrough is confined to the exposed surface area of the underlying topography but not on the sidewalls of the apertures through the dielectric layer. The sacrificial layers (and overlying metal plate) are then removed leaving only the patterned conformed dielectric layer and the deposited metal. The main body portion of the interconnect structure is now plated onto the deposited metal pattern to a thickness in the apertures of the dielectric which is slightly below the top surface of the dielectric layer. Thereafter, a second, thin dielectric layer is non-selectively conformally deposited over the entire structure. Contact vias for a second layer of metal to be formed over the top surface of the second dielectric layer are selectively etched through this second dielectric layer to expose surface portions of the underlying plated metal.

Self-planarized gold interconnect layer

The inability of conventional adhesion/diffusion barrier Ti-TiN laminates to secure a narrow linewidth electrodeposited gold layer to a silicon structure and prevent unwanted gold diffusion during anneal cycles at temperatures greater than 370.degree. C. for substantial periods of time is overcome by the addition of a medium thickness (.gtoreq.1,500.ANG.) layer of tungsten over the exposed silicon prior to formation of the titanium/titanium nitride laminate structure.

Multiple layer, tungsten/titanium/titanium nitride adhesion/diffusion

Adhesion of gold interconnects to silicon dioxide is achieved by forming, through chemical vapor deposition, or plasma enhanced chemical vapor deposition, an extremely thin film of titanium over the entirety of exposed surfaces of an integrated circuit structure on which the gold lines are disposed and over which a silicon dioxide layer is to be formed. This extremely thin film of titanium is then exposed to a flow of an oxidizer to convert the titanium to a film of (insulating) titanium oxide which, unlike gold, strongly adheres to silicon dioxide. Silicon dioxide is then deposited on the titanium oxide film. In the resulting multilayer interconnect structure, the insulator consists of a layer of silicon dioxide adhering to a thin adhesive layer of TiO.sub.x or SiOx-TiO.sub.y at those locations whereat no gold lines are formed, while, on the gold conductor lines, the insulator contains silicon dioxide formed on a thin adhesive layer of SiO.sub.y -TiO.sub.x atop a TiO.sub.y -TiAu interface.

Method of ensuring adhesion of chemically vapor deposited oxide to gold

Adhesion of gold interconnects to silicon dioxide is achieved by forming, through chemical vapor deposition, or plasma enhanced chemical vapor deposition, an extremely thin film of titanium over the entirety of exposed surfaces of an integrated circuit structure on which the gold lines are disposed and over which a silicon dioxide layer is to be formed. This extremely thin film of titanium is then exposed to a flow of an oxidizer to convert the titanium to a film of (insulating) titanium oxide which, unlike gold, strongly adheres to silicon dioxide. Silicon dioxide is then deposited on the titanium oxide film. In the resulting multilayer interconnect structure, the insulator consists of a layer of silicon dioxide adhering to a thin adhesive layer of TiO.sub.x or SiOx--TiO.sub.y at those locations whereat no gold lines are formed, while, on the gold conductor lines, the insulator contains silicon dioxide formed on a thin adhesive layer of SiO.sub.y --TiO.sub.x atop a TiO.sub.y --TiAu interface.

To securely attach a narrow line width electrodeposited layer of gold to an underlying semiconductor structure a thin multiphase adhesion film of nitrogen-modified titanium is formed between a titanium nitride diffusion barrier layer and an overlying gold seed layer. This additional layer nitrogen-modified titanium layer provides a titanium base to ensure adhesion of the gold, yet contains sufficient nitrogen interstitially dispersed in the thin titanium film to prevent formation of unetchable gold-titanium compounds.

Multiple-layer, multiple-phase titanium/nitrogen adhesion/diffusion

Formation of a metallic interconnect pattern in submicron geometry architectures, without the photoresist being lifted off the substrate and resulting in the deposited metal being electroplated therebeneath, is achieved by a combination of a toughened-skin photoresist and pulsed electroplating. For toughening the skin of the photoresist and thereby enhancing its ability to withstand encroachment of the electrodeposited metal, the photoresist layer is illuminated with ultraviolet radiation. After the UV-irradiated photoresist has been allowed to cool, the resulting structure is placed in an electroplating bath, with appropriate electrodes disposed in the bath and connected to a said layer on the wafer for the deposition of the interconnect metal. The electrode differential is pulsed to provide a low frequency plating current through which the conductor metal is plated onto the seed metal on the wafer, as defined by the pattern of the toughened photoresist. After a prescribed, controlled electrodeposition interval during which the interconnect conductor has been plated to a desired level by the pulsed electroplating current, the wafer is removed from the bath and the photoresist layer is etched off, to leave only the electrodeposited interconnect layer and the underlying base (seed) metal. The exposed base metal is then etched leaving only the desired electrodeposited interconnect pattern.

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Durham, NC, United States of America

Jimmy C Black