Samsung Electronics Co., Ltd.

Jimin Choi

Yeonjin Lee

Jongmin Lee

Jung-Hoon Han

Jihoon Chang

Yoosang Hwang

Keunnam Kim

Yong Kwan Kim

Myeong-Dong Lee

Minjung Choi

Juik Lee

Jeonil Lee

Changhyun Cho

Dongryul Lee

Minseong Choi

Jong-Min Lee

Minsoo Park

Seungjun Lee

Hyeon-Woo Jang

Byungkook Yoo

Mingu Chang

Inyoung Lee

Jeon Il Lee

Joongwon Shin

Jeongjae Bang

Gyeongdam Baek

Younboo Jung

Kunjin Ryu

Hujong Lee

Hyungsik Um

Sangjune Bae

Hyeonhui Cho

A semiconductor device according to the disclosure includes a substrate, a transistor connected to the substrate, and a wiring structure including contact wirings electrically connected to the transistor. The wiring structure further includes a first wiring insulating layer, a first material layer contacting the first wiring insulating layer, a second material layer contacting the first material layer, and a second wiring insulating layer contacting the second material layer. The first material layer includes SiN, and the second material layer includes SiCN. A dielectric constant of the first wiring insulating layer is greater than a dielectric constant of the second wiring insulating layer.

Semiconductor device including multi-capping layer and method for manufacturing the same

A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.

Semiconductor devices including a through-hole electrode

A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

Semiconductor device

A steering device for an OHT according to some example embodiments of the present inventive concepts includes: an LM block; a steering plate fixedly installed to the LM block and provided with an insertion groove; a link installed in the insertion groove of the steering plate and tilted; a main bearing having an outer circumferential surface in contact with the link to reduce friction when the link is tilted; and a guide roller rotatably installed on a protrusion protruding from the link.

Steering devices for OHT

A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

Semiconductor device including through-silicon via and method of forming the same

A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

Thermal pad, semiconductor chip including the same and method of manufacturing the semiconductor chip

A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

Detection pad structure for analysis in a semiconductor device

An apparatus for storage of a carrying material, includes: a body frame; a plurality of loading members installed on the body frame and disposed such that a carrying material forms a plurality of layers in upper and lower directions; a driving unit connected to at least one of the plurality of loading members; and an auxiliary coupling unit provided in a portion of the plurality of loading members for attachment and detachment to and from a neighboring loading member, wherein the plurality of loading members are provided with a plurality of first loading members fixedly installed at a lower end portion of the body frame, and a plurality of second loading members disposed above the first loading member and movably installed on the body frame, wherein the driving unit is connected to at least one of the plurality of second loading members, wherein the auxiliary coupling unit includes an electromagnet installed at one end of the second loading members, and a magnetic body installed at the other end of the second loading members and the body frame to correspond to the electromagnet.

Apparatus for storage of carrying material

The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Semiconductor device and method of fabricating the same

A storage system includes a storage device and a transfer device. The storage device includes a guide bar, a plurality of upper shelves connected to the guide bar, the plurality of upper shelves storing a material to be transferred, a plurality of lower shelves disposed under the plurality of upper shelves, the plurality of lower shelves storing the material, a plurality of guides connected to the plurality of upper shelves, and a shelf returning device connected to a selected upper shelf from among the plurality of upper shelves. The transfer device includes a body, a drive module attached to the body, the drive module moving the transfer device to be adjacent to the storage device, a handling module attached to the body, the handling module handling the material, and a shelf moving module attached to the body or the handling module, the shelf moving module contacting a selected guide from among the plurality of guides.

Storage system including shelf moving module

According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

Semiconductor devices and methods of fabricating the same

Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

Growing community of inventors

Hwaseong-si, South Korea

Jimin Choi