Via Technologies, Inc.

Jim Xu

John Wakefield Brothers

Zahid Hussain

Mike Hong

Li Liang

Dong Zhou

Minjie Huang

Wen Chen

Sibyl Shao

Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.

VPU with programmable core

Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M&#xd7;N and an n&#xd7;n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n&#xd7;n block and to one block contained within the M&#xd7;N pixel block and horizontally offset within the n&#xd7;n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n&#xd7;n pixel block and to one block contained within an M&#xd7;N block and horizontally offset within the n&#xd7;n block. M, N, and n are integers.

Systems and methods of improved motion estimation using a graphics processing unit

Disclosed are systems and methods for debugging and analyzing graphics hardware designs. Hardware designs are represented by a software model implemented in a programming language. Graphics operations can be executed in the software model as well as in reference software models to allow a user to analyze the accuracy of a graphics hardware design and/or a device driver implementation.

Systems and methods for graphics hardware design debugging and verification

Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the organized texture map data from the texture management unit.

Systems and methods for storing texture map data

Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for texture filtering within the graphics processing unit, partitioning the texture data into banks, performing a bank swizzle operation on the banks, and writing the banks of data to the L2 cache.

Systems and methods for performing a bank swizzle operation to reduce bank collisions

Systems and methods for border color handling in a graphics processing unit are disclosed. In one embodiment, the system includes a border color register that stores at least one border color pointer. A border color pointer indicates an address in an external memory at which border color information is located. Border color information is populated within external memory and retrieved by the texture cache controller if the texture filter unit requires a border color for texture mapping operations.

Growing community of inventors

San Jose, CA, United States of America

Jim Xu